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intel/genxml: Do small fixes in gfx20 definition of STATE_COMPUTE_MODE

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Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30796>
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José Roberto de Souza 2024-08-22 09:25:22 -07:00 • committed by Marge Bot
parent 3efba707bf
commit 2483f8f7cd
1 changed files with 4 additions and 3 deletions
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7
src/intel/genxml/gen20.xml
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@ -1139,12 +1139,13 @@
<value name="Max 40" value="4" />
<value name="Max 32" value="5" />
</field>
<field name="Z Async Throttle settings" start="35" end="36" type="uint">
<field name="Z Async Throttle settings" start="35" end="36" type="uint" prefix="ZATS">
<value name="Defer to Async Compute Thread Limit" value="0" />
<value name="Max 32" value="1" />
<value name="Max 40" value="2" />
<value name="Max 48" value="3" />
</field>
<field name="Pixel Async Compute Thread Limit" start="39" end="41" type="uint" prefix="PACTL">
<field name="Async Compute Thread Limit" start="39" end="41" type="uint" prefix="ACTL">
<value name="Disabled" value="0" />
<value name="Max 2" value="1" />
<value name="Max 8" value="2" />
@ -1159,7 +1160,7 @@
<field name="Z Pass Async Compute Thread Limit Mask" start="48" end="50" type="uint" />
<field name="Mask1" start="48" end="63" type="uint" />
<field name="Z Async Throttle settings Mask" start="51" end="52" type="uint" />
<field name="Pixel Async Compute Thread Limit Mask" start="55" end="57" type="uint" />
<field name="Async Compute Thread Limit Mask" start="55" end="57" type="uint" />
<field name="EU Thread Scheduling Mode Override Mask" start="61" end="62" type="uint" />
<field name="Large GRF Mode Mask" start="63" end="63" type="bool" />
<field name="Midthread Preemption Delay Timer" start="64" end="66" type="uint">