Discard block is always added to the block list after translation from NIR,
so we can just assign it an index that equals to block list size.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33754>
This saves us jumping through an entrypoing just to fetch a uint64_t.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33897>
On a7xx, const registers should be loaded via the preamble instead of
uploaded by the driver to the const state. This commit implements this
by adding a new pass that emits the consts created by ir3_cp to a
sequence of stc instructions in the preamble.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
On a7xx, the immediates that get promoted to const registers will be
initialized in the preamble instead of being part of the const state. So
technically, we won't need the immediate state that is part of the const
state anymore on a7xx. However, it is still a convenient place for
ir3_cp to store the immediates that should be promoted to const
registers before they are lowered to the preamble.
This causes one issue: the binning pass isn't allowed to modify the
const state while it's perfectly fine for it to use different immediates
compared to the non-binning pass on a7xx. Even pre-a7xx this is fine as
long as the size of the immediate buffer is the same.
To allow the binning pass to modify its immediate state while keeping
its const state immutable, this commit moves the fields related to
immediates into a new struct. Runtime checks are added to enforce that
the size of the immediate buffer is the same for the binning and
non-binning variant pre-a7xx.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
When merging multiple instructions into one rpt instruction, the false
deps of the rpt instruction should be the union of the false deps of its
parts.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 4c4366179b ("ir3: add post-RA pass to merge repeat groups into rptN instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
Creating STC is complicated since we might need to use a1.x for
addressing. Extract the current code into a helper so that it can be
used elsewhere.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
Removing duplicates is now supported by ir3_cse so the hash table is
unnecessary. Removing it will make it easier to create instructions
using a1.x without having access to ir3_context.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32454>
The AttrAccess structure provided inputs for similar instructions, some
inputs were used only in a subset of instructions, needing asserts and
dummy values.
This commit flattens the struct directly in the instructions removing
the unused fields and cleaning up the code.
Signed-off-by: Lorenzo Rossi <snowycoder@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33899>
Generalization for the following:
1. pass in the scaler output alignment requirement to segment number determination function
2. parameter validation hook
Signed-off-by: Navid Assadian <Navid.Assadian@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
[WHY]
The full range needs to have the same brightness normalization like the
studio range.
[HOW]
Apply the same normalization.
Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Reviewed-by: Tomson Chang <Tomson.Chang@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
[WHY]
Studio signal has an offset.
[HOW]
Subtract that offset.
Signed-off-by: Tiberiu Visan <Tiberiu.Visan@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
Reformat index variables to indicate loop specifics and update enum to match formatting guide.
Signed-off-by: Brendan Steve Leder <Brendansteve.Leder@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Evan Damphousse <Evan.Damphousse@amd.com>
Acked-by: Alan Liu <Haoping.Liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33833>
Currently spilling code operates on individual ops rather than on
instructions, and as a result it may create a redundant load_temp op if
an instruction references spilling register several times.
Similarly, it creates multiple stores if there are multiple ops in the
instruction that write different components of the register.
Check whether the instruction already contains a necessary load_temp or
store_temp and reuse it if possible.
shader-db:
total instructions in shared programs: 27718 -> 27673 (-0.16%)
instructions in affected programs: 2786 -> 2741 (-1.62%)
helped: 18
HURT: 0
helped stats (abs) min: 1 max: 8 x̄: 2.50 x̃: 1
helped stats (rel) min: 0.39% max: 5.33% x̄: 2.05% x̃: 0.80%
95% mean confidence interval for instructions value: -3.70 -1.30
95% mean confidence interval for instructions %-change: -3.09% -1.01%
Instructions are helped.
total loops in shared programs: 4 -> 4 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 390 -> 381 (-2.31%)
spills in affected programs: 145 -> 136 (-6.21%)
helped: 9
HURT: 0
total fills in shared programs: 1210 -> 1174 (-2.98%)
fills in affected programs: 149 -> 113 (-24.16%)
helped: 9
HURT: 0
LOST: 0
GAINED: 0
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33753>
we shouldn't need any of this anymore. I cleared out similar gunk from Asahi, we do the same for Panfrost here.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
this is slightly less weird I think.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
this contains two behaviour changes:
* NDEBUG no longer set in debug builds (so asserts work in debug, but are still
stripped out in release as expected).
* macro map set properly for assertions to be reported with proper paths.
together this makes assertions do the right thing on Intel and brings us in
alignment with asahi+panfrost
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
this will let us unify behaviour across drivers a bit more.
no functional change here. (intel is specifically excluded to avoid a functional
change.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33879>
There's already code to verify that any compacted instruction
that we produce is equivalent to the original uncompacted
instruction -- including detailed output if it fails.
This patch enables this verification in debug build and will
abort in case it fails.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33821>
nir_lower_int64 doesn't know how to lower 64-bit imul reductions and
scans. Lowering subgroup operations first leaves us with just 64-bit
ballot and read_invocation, which are easily lowered.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
* ballot{,_relaxed}'s src[0] must always be a 32-bit value.
* read_invocation's src[0] must always be at most 32-bit value. While
the HW instruction always operates on a 32-bit value, it's important
to remember that it's just a data movement operation, so garbage in
the high bits of a 32-bit value representing a narrower value don't
present an issue.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33365>
