Commit graph

13292 commits

Author SHA1 Message Date
Dave Airlie
68477ae7c0 genxml: add av1 fields
Co-authored-by: Hyunjun Ko <zzoon@igalia.com>
- Remove HuC pipeline params of VD_PIPELINE_FLUSH
- Fix length of AVP_PIPE_MODE_SELECT, AVP_PIC_STATE, AVP_PIPE_BUF_ADDR_STATE

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32775>
2025-01-10 21:45:04 +00:00
Dave Airlie
6a28e7a6c7 anv: add default av1 tables from media-driver
Co-authored-by: Hyunjun Ko <zzoon@igalia.com>
- Change to C-style comment.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32775>
2025-01-10 21:45:04 +00:00
Caio Oliveira
7fadd864dd intel/elk: Fix typo in assertion
Just assert that the array will fit whatever the MAX is for a given
Gfx version.

Fixes: 172c1ab984 ("intel/elk: Add ELK_MAX_MRF_ALL for static allocating arrays")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32978>
2025-01-10 20:16:59 +00:00
Michael Cheng
c3c05ffb5f intel : Expose Shader hashes for utrace and Perfetto
This patch exposes shader hashes (computes and draws) to Perfetto and
utrace. By including these hashes in traces, developers can correlate
compute and draw calls with their assoicated ASM dumps when analyzing
the traces.

To achieve this, intel_tracepoint.py has been reworked to preprocess
tracepoint arguments dynamically. Any argument containing "hash" in its
variable name is now forrmated as hexadecimal before being passed to the
tracepoint definition.

Signed-off-by: Michael <michael.cheng@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32708>
2025-01-10 17:38:16 +00:00
Caio Oliveira
c9e667b7ad intel/elk: Remove uses of VLAs
Was causing trouble in some build configurations, we don't really need
them.  Unless there's a good reason, defaults to use ralloc for
consistency with the larger codebase.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
2025-01-10 07:05:35 +00:00
Caio Oliveira
172c1ab984 intel/elk: Add ELK_MAX_MRF_ALL for static allocating arrays
Replace usage of variable length arrays.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
2025-01-10 07:05:35 +00:00
Caio Oliveira
4d43ee0dd6 intel/brw: Remove uses of VLAs
Was causing trouble in some build configurations, we don't really need
them.  Use ralloc for consistency.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
2025-01-10 07:05:35 +00:00
Caio Oliveira
faf4c35b74 intel/compiler: Use linear allocator for ACP trees in copy-prop
Replace usage of variable length array.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
2025-01-10 07:05:35 +00:00
Caio Oliveira
e6a3770433 intel/compiler: Use INFINITY spill cost to represent no_spill
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>
2025-01-10 07:05:35 +00:00
Sagar Ghuge
710624fcc0 anv: Use 3DSTATE_URB_ALLOC_* instructions
Use 3DSTATE_URB_ALLOC_* instruction to program URB for multislice device
config.

In case only one slice is available in the device, SliceN fields will be
ignored by HW.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
2025-01-09 21:26:40 +00:00
Sagar Ghuge
604a384e97 blorp: Use 3DSTATE_URB_ALLOC_* instructions
Use 3DSTATE_URB_ALLOC_* instruction to program URB for multislice device
config.

In case only one slice is available in the device, SliceN fields will be
ignored by HW.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
2025-01-09 21:26:40 +00:00
Sagar Ghuge
0bca8da981 intel/genxml: Update URB related instructions and structures
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32736>
2025-01-09 21:26:40 +00:00
Lionel Landwerlin
58b604abdf intel: fix generation shader on Gfx9
This probably interacts badly with the LLVM17+ opaque pointer
workaround. Hopefully I can move this all over Alyssa's pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b52e25d3a8 ("anv: rewrite internal shaders using OpenCL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12413
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32958>
2025-01-09 18:12:47 +00:00
Lionel Landwerlin
08e82b28e8 anv: use the correct MOCS for depth destinations
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31778>
2025-01-09 17:47:27 +00:00
José Roberto de Souza
1d1d5653ac anv: Check VkResult main batch buffer before start companion batch buffer
It could run the companion batch buffer even if the main batch buffer
failed, that was possible to happen in i915 and Xe KMD.

In case the main context/queue is banned and companion is not it could
still return that submission was properly start what was not.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32850>
2025-01-09 13:47:28 +00:00
José Roberto de Souza
4c6194cae0 anv: Check VkResult of perf query batch buffer
On i915 it could be executing the main batch buffer in
i915_queue_exec_locked() even if the perf query batch buffer failed.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32850>
2025-01-09 13:47:28 +00:00
Valentine Burley
288249811d anv/ci: Increase anv-tgl-angle parallelism to 2
We have enough DUTs available, so increase parallelism to ensure
that we stay within the 10-minute time limit.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32864>
2025-01-09 12:24:34 +00:00
Vinson Lee
83809f06a7 intel/elk: Fix assert with side effect
Fix defect reported by Coverity Scan.

Side effect in assertion (ASSERT_SIDE_EFFECT)
assert_side_effect: Argument ++eot_count of assert() has a side effect.
The containing function might work differently in a non-debug build.

Fixes: ebd6738260 ("intel/elk/chv: Implement WaClearArfDependenciesBeforeEot")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32884>
2025-01-09 04:07:42 +00:00
Matt Turner
89da5a9626 intel/decoder: Avoid duplicate symbols when expat is not available
Fixes: 0669210ef4 ("intel/decoder: Add ELK support")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12335
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32732>
2025-01-08 18:58:35 +00:00
Kenneth Graunke
35f175301d brw: Fix vectorizer hole_size condition after signedness change
Marek recently changed hole_size to be signed, rather than unsigned.
A negative hole_size means that the two loads overlap - and thus are
prime candidates to be combined.

My original hole_size handling was:

   if hole_size > 4 * (8 - low->num_components) then don't vectorize

For non-overlapping loads, this worked: NIR's largest vector is vec16,
and if low was already a vec16, combining it with anything would exceed
that, so it'd never be considered.  That meant low would always be a
vec8 or less, so (8 - low->num_components) was a positive number.

Now that we see overlapping loads, we can see a vec16 low, vec4 high,
and also a negative hole size, giving us fun comparisons like:

   -16 > 4 * (8 - 16)   =>   -16 > -32   => true, don't vectorize

Which is absolutely the wrong thing to do, because the high load's data
is entirely included within the former load's data.

The idea here was to make sure the second load would be able to pack at
least one component into the first's V8 result.  But even this isn't the
best, because...even if it's simply adjacent, doing one V16 load is more
efficient than requesting two back to back V8 loads.

So, we just simplify down to a static check: if there's an entire V8 of
hole, don't vectorize.  This already won't happen because the core pass
has max_hole set to 28 bytes (7 32-bit components), but that could
change based on the needs of other drivers, so let's be defensive.

fossil-db results on Alchemist:

   Instrs: 161533978 -> 161295137 (-0.15%); split: -0.20%, +0.05%
   Subgroup size: 8092544 -> 8092568 (+0.00%)
   Send messages: 7915233 -> 7844503 (-0.89%); split: -0.94%, +0.05%
   Cycle count: 16577700697 -> 16702609256 (+0.75%); split: -0.59%, +1.35%
   Spill count: 72338 -> 67226 (-7.07%); split: -7.36%, +0.29%
   Fill count: 134058 -> 125980 (-6.03%); split: -6.83%, +0.80%
   Scratch Memory Size: 4092928 -> 3786752 (-7.48%); split: -7.53%, +0.05%
   Max live registers: 33031460 -> 32945994 (-0.26%); split: -0.27%, +0.01%
   Max dispatch width: 5778384 -> 5778536 (+0.00%); split: +0.26%, -0.26%
   Non SSA regs after NIR: 179809505 -> 152735471 (-15.06%); split: -15.08%, +0.03%

Fixes: c21bc65ba7 ("nir/opt_load_store_vectorize: make hole_size signed to indicate overlapping loads")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32932>
2025-01-08 00:19:54 +00:00
Sagar Ghuge
33d9a685a5 anv: Add pipelined coarse pixel state
3DSTATE_CPS_POINTERS is deprecated on PTL, so let's switch to
3DSTATE_COARSE_PIXEL to deliver CPS state as pipelined state.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32737>
2025-01-07 23:53:44 +00:00
Sagar Ghuge
9d33443d7b intel/genxml: Add coarse pixel related changes
This change adds CPS related new state instruction, structure and
enum.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32737>
2025-01-07 23:53:44 +00:00
Caio Oliveira
868016d92c intel/brw/xe2+: Do not use $.dst or $.src SWSB annotations in SENDs
When a SEND instruction is a EOT, the scoreboard lowering will not
allocate a new SBID for it, since nothing needs to wait for it.  In
Gfx12 this allowed the SEND to get out-of-order $.dst or $.src
dependencies.

Starting on Xe2+ this is not supported anymore, in favor of supporting
more combined modes.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32712>
2025-01-07 22:23:59 +00:00
Tapani Pälli
1cc17e9ce9 intel/compiler: take reg_unit size into account with ubo ranges
Fixes: 1ab4fe2dd6 ("brw: Don't shrink UBO push ranges in the backend")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12423
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32925>
2025-01-07 21:38:06 +00:00
Sagar Ghuge
385977955b intel: Set correct maxComputeSharedMemorySize for Xe3+
For Xe3+, set preferred SLM and SLM per threadgroup size.

Bspec: 73211
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32872>
2025-01-07 07:06:09 +00:00
Chia-I Wu
dd0f8cc7de hasvk: use common calibrated timestamp support
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32689>
2025-01-07 03:39:29 +00:00
Chia-I Wu
83dec767da anv: use common calibrated timestamp support partially
Use the common GetPhysicalDeviceCalibrateableTimeDomainsKHR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32689>
2025-01-07 03:39:29 +00:00
José Roberto de Souza
7ac9ac0f93 anv: Allow larger SLM sizes for task and mesh shader
It was hard-coded to 64k but Xe2 platforms and newer supports
larger SLM sizes.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Cc: mesa-stable
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32874>
2025-01-06 18:31:20 +00:00
Kenneth Graunke
4ab04799ee brw: Delete assign_constant_locations and push_constant_loc[]
The push_constant_loc[] array is always an identity mapping these days,
so it's kind of pointless.  Just use the original uniform number and
skip the unnecessary "remap" step.  With that gone, and shrinking UBO
ranges gone, assign_constant_locations() is now empty and can be removed
as well.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Kenneth Graunke
93e186e1a4 brw: Delete pull constant lowering
Now that we never shrink ranges in the backend, we never lower push
constants to pull constants late in the backend either.  get_pull_loc
will never return true, and so all of brw_lower_constant_loads becomes
a noop.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Kenneth Graunke
1ab4fe2dd6 brw: Don't shrink UBO push ranges in the backend
Back in the bad old days (vec4?) we had a bunch of smarts in the backend
to dead code eliminate unused vector components and re-pack regular
uniforms, so we really couldn't decide how much data we were pushing
until very late in the backend.  Nowadays we have none of that - we do
all of our elimination and packing in NIR.  anv shrinks ranges to deal
with Vulkan API push constants, and iris treats everything as a UBO and
as of the previous commit will also shrink appropriately.

So we don't need to do this anymore...which will let us simplify quite
a bit of code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Kenneth Graunke
583ad35455 brw: Limit maximum push UBO ranges to 64 registers in the NIR pass.
anv already does this limiting, since it needs to handle non-UBO push
constants as well.  iris treats everything as a UBO, but doesn't have
a limiter and was relying on the backend to handle it.

Do this in the NIR pass so that we can eliminate the backend code.
It's not necessary for anv, but handling it here is simple and less
error prone for iris, which calls this in a number of places.  We know
we need to limit things to this much; anv can limit more if needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32841>
2025-01-06 12:45:47 +00:00
Tapani Pälli
72351afe24 anv: handle mesh in sbe_primitive_id_override
This prevents crashes seen in some upcoming cts tests.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32861>
2025-01-06 08:41:18 +00:00
Hyunjun Ko
5ecea6ec4a anv: handle negative value of slot index for h265 decoding.
Fixes: 8d519eb5 ("anv: add initial video decode support for h265")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32823>
2025-01-06 01:02:14 +00:00
Hyunjun Ko
168298b891 anv: Enable remapping picture ID
Fix to handle 16 refs.

v1. handle the case where a slot index is negative.
(Lionel Landwerlin <lionel.g.landwerlin@intel.com>)

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32823>
2025-01-06 01:02:14 +00:00
Hyunjun Ko
9221feaf79 anv: define ANV_VIDEO_H264_MAX_DPB_SLOTS
prep work for remapping slot ids for h264 decoding.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32823>
2025-01-06 01:02:13 +00:00
Lionel Landwerlin
98cdb9349a anv: ensure null-rt bit in compiler isn't used when there is ds attachment
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 15987f49bb ("anv: avoid setting up a null RT unless needed")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12396
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32867>
2025-01-03 23:12:22 +00:00
Caio Oliveira
6968794c50 intel/brw: Add missing bits in 3-src SWSB encoding for Xe2+
Fix invalid SWSB annotation in dEQP-VK.glsl.builtin.precision.mix.mediump.vec4 for LNL.

Fixes: 4a24f49b57 ("intel/compiler/xe2: Implement codegen of three-source instructions.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32846>
2025-01-03 21:19:26 +00:00
Lionel Landwerlin
1448778385 anv: rework tbimr push constant workaround
We'll want to know about the empty push constant for device generated
commands. It's easier if the information is stored in
anv_pipeline_bind_map::push_ranges[].

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32828>
2025-01-03 11:48:42 +00:00
Lionel Landwerlin
6281b207db anv: add tracepoints timestamp mode for empty dispatches
When the runtime is going to potentially emit no dispatch, we need to
have a way to capture a timestamp. Add a new flag for this to tell
whether we don't have a HW instruction to capture the timestamp and
rely on MI_STORE_REGISTER_MEM instead.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: de00fe3f66 ("anv: add BVH building tracking through u_trace")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12382
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32835>
2025-01-03 10:36:49 +00:00
Dylan Baker
d9429229cf intel/tests: Fix missing assignment of error condition
Coverity notices that `err` might be used uninitialized, which is true
as we don't assign the value we want to check! Fix that assignment so
the EXPECT_EQ macro does what we expect.

CID: 1635272
Fixes: 6b931a68c7 ("intel/common: Implement Xe KMD in mi_builder tests")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32849>
2025-01-03 00:53:49 +00:00
Dylan Baker
5420fc16d6 intel/tests: Fix coverity warning about possibly leaked memory
If the assert were to fail the memory would leak, which is pretty
harmless in a unit test, but the fix is trivial.

CID: 1635429
Fixes: 6b931a68c7 ("intel/common: Implement Xe KMD in mi_builder tests")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32849>
2025-01-03 00:53:49 +00:00
Caio Oliveira
e1aebf8a0c intel/brw: Remove 'fs' prefix from passes and related functions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32813>
2025-01-02 18:11:05 +00:00
Caio Oliveira
25384dccc0 intel/brw: Remove 'fs' prefix from passes filenames
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32813>
2025-01-02 18:11:05 +00:00
Lionel Landwerlin
6fb2d3b163 anv: limit the memcpy data for push constants
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32824>
2025-01-02 16:48:04 +00:00
Marek Olšák
c21bc65ba7 nir/opt_load_store_vectorize: make hole_size signed to indicate overlapping loads
A negative hole size means the loads overlap. This will be used by drivers
to handle overlapping loads in the callback easily.

Reviewed-by: Mel Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32699>
2025-01-01 00:03:55 +00:00
Sagar Ghuge
76e85df2d2 anv: Switch to ANISOTROPIC_FAST filter mode
Same thing as ANISOTROPIC including all restrictions except HW is
allowed to take liberties with precision to speed things up, Currently
only has an affect on formats of type *_sRGB.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32738>
2024-12-31 21:49:41 +00:00
Sagar Ghuge
15063d79d3 intel/genxml: Update SAMPLER_STATE structure
Add new ANISOTROPIC_FAST filter mode value to the Min/MagModeFilter
field.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32738>
2024-12-31 21:49:41 +00:00
Valentine Burley
6b0d551e8b angle/ci: Update expectations
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32749>
2024-12-31 08:03:46 +00:00
Caio Oliveira
056b14b882 intel/brw: Move two NIR passes to brw_nir.c
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32799>
2024-12-30 20:18:23 +00:00