intel/brw: Remove uses of VLAs

Was causing trouble in some build configurations, we don't really need
them.  Use ralloc for consistency.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Antonio Ospite <None>
Reviewed-by: Kenneth Graunke <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32916>

src/intel/compiler/brw_fs_reg_allocate.cpp

@@ -48,7 +48,7 @@ void
 brw_assign_regs_trivial(fs_visitor &s)
 {
    const struct intel_device_info *devinfo = s.devinfo;
-   unsigned hw_reg_mapping[s.alloc.count + 1];
+   unsigned *hw_reg_mapping = ralloc_array(NULL, unsigned, s.alloc.count + 1);
    unsigned i;
    int reg_width = s.dispatch_width / 8;
 
@@ -75,6 +75,7 @@ brw_assign_regs_trivial(fs_visitor &s)
       s.alloc.count = s.grf_used;
    }
 
+   ralloc_free(hw_reg_mapping);
 }
 
 extern "C" void
@@ -918,11 +919,7 @@ void
 fs_reg_alloc::set_spill_costs()
 {
    float block_scale = 1.0;
-   float spill_costs[fs->alloc.count];
-
-   for (unsigned i = 0; i < fs->alloc.count; i++) {
-      spill_costs[i] = 0.0;
-   }
+   float *spill_costs = rzalloc_array(NULL, float, fs->alloc.count);
 
    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
     * spill/unspill we'll have to do, and guess that the insides of
@@ -996,6 +993,8 @@ fs_reg_alloc::set_spill_costs()
    }
 
    have_spill_costs = true;
+
+   ralloc_free(spill_costs);
 }
 
 int
@@ -1240,7 +1239,7 @@ fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all)
     * regs in the register classes back down to real hardware reg
     * numbers.
     */
-   unsigned hw_reg_mapping[fs->alloc.count];
+   unsigned *hw_reg_mapping = ralloc_array(NULL, unsigned, fs->alloc.count);
    fs->grf_used = fs->first_non_payload_grf;
    for (unsigned i = 0; i < fs->alloc.count; i++) {
       int reg = ra_get_node_reg(g, first_vgrf_node + i);
@@ -1260,6 +1259,8 @@ fs_reg_alloc::assign_regs(bool allow_spilling, bool spill_all)
 
    fs->alloc.count = fs->grf_used;
 
+   ralloc_free(hw_reg_mapping);
+
    return true;
 }
 

src/intel/compiler/brw_lower_simd_width.cpp

@@ -503,7 +503,9 @@ emit_unzip(const fs_builder &lbld, fs_inst *inst, unsigned i)
       const unsigned num_components = inst->components_read(i);
       const brw_reg tmp = lbld.vgrf(inst->src[i].type, num_components);
 
-      brw_reg comps[num_components];
+      assert(num_components <= NIR_MAX_VEC_COMPONENTS);
+      brw_reg comps[NIR_MAX_VEC_COMPONENTS];
+
       for (unsigned k = 0; k < num_components; ++k)
          comps[k] = offset(src, inst->exec_size, k);
       lbld.VEC(tmp, comps, num_components);

src/intel/compiler/brw_schedule_instructions.cpp

@@ -847,7 +847,7 @@ instruction_scheduler::setup_liveness(cfg_t *cfg)
       }
    }
 
-   int payload_last_use_ip[hw_reg_count];
+   int *payload_last_use_ip = ralloc_array(NULL, int, hw_reg_count);
    s->calculate_payload_ranges(true, hw_reg_count, payload_last_use_ip);
 
    for (unsigned i = 0; i < hw_reg_count; i++) {
@@ -862,6 +862,8 @@ instruction_scheduler::setup_liveness(cfg_t *cfg)
             BITSET_SET(hw_liveout[block], i);
       }
    }
+
+   ralloc_free(payload_last_use_ip);
 }
 
 void