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58 commits

Author SHA1 Message Date
Kenneth Graunke
c0a32af125 brw: Use correct builder size for MEMORY_FENCE/INTERLOCK virtual opcodes
brw_memory_fence() overrides the instructions generated by the
MEMORY_FENCE or INTERLOCK opcodes to be force_writemask_all with
exec_size == 1.  But the IR was emitting it in SIMD8 (regardless
of dispatch width).  Instead, just emit the IR as SIMD1/NoMask so
the IR matches what we actually generate.  Have size_written indicate
that the entire destination is written, however, as it is ultimately
going to be a SEND that writes a whole register.

We were also using a UD register for the source of
FS_OPCODE_SCHEDULING_FENCE when the generator overrides it to UW,
so just specify UW in the IR as well so that they line up.

Also add validation for MEMORY_FENCE/INTERLOCK that we've done the
exec_size and masking right in the IR.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
2025-02-08 01:07:22 +00:00
Kenneth Graunke
accef5e8f5 brw: Replace fs_inst::target field with logical FB read/write sources
We can just specify this as a source to the logical FB read/write
opcodes.  Notably FB reads had no sources before; now they have one.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
2025-02-08 01:07:22 +00:00
Kenneth Graunke
7390d6189c brw: Replace fs_inst::pi_noperspective with a logical control source
We already have logical pixel interpolator messages that get lowered
to send messages.  We can just add an extra boolean source to those
opcodes rather than sticking a opcode-specific boolean in the generic
fs_inst data structure.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
2025-02-08 01:07:22 +00:00
Kenneth Graunke
168ac07ffd brw: Eliminate fs_inst::shadow_compare
brw_lower_logical_sends can just check for the TEX_LOGICAL_SRC_SHADOW_C
source; we don't need a generic instruction bit for this.  We used to
have one because this was handled in the generator for older hardware
before the advent of logical opcode lowering.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
2025-02-08 01:07:22 +00:00
Caio Oliveira
f82bcd56fc intel/brw: Add functions to allocate VGRF space
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33334>
2025-02-06 08:33:03 -08:00
Caio Oliveira
ea87bab4ce intel/brw: Remove 'using namespace brw' directives
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33418>
2025-02-06 07:58:55 -08:00
Caio Oliveira
92085e7bab intel/brw: Remove 'fs' prefix from brw_from_nir functions
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Dylan Baker <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33330>
2025-02-03 23:08:11 +00:00
Caio Oliveira
1332d84500 intel/brw: Rename file brw_fs_nir.cpp to brw_from_nir.cpp
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Dylan Baker <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33330>
2025-02-03 23:08:11 +00:00
Renamed from src/intel/compiler/brw_fs_nir.cpp (Browse further)