fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-06 02:20:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

brw: Replace fs_inst::target field with logical FB read/write sources

Browse source 
We can just specify this as a source to the logical FB read/write
opcodes.  Notably FB reads had no sources before; now they have one.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33297>
This commit is contained in:
Kenneth Graunke 2025-01-16 15:36:36 -08:00 • committed by Marge Bot
parent 32dd722ff3
commit accef5e8f5
6 changed files with 21 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/intel/compiler/brw_compile_fs.cpp
View file

@ -21,7 +21,8 @@
static brw_inst *
brw_emit_single_fb_write(fs_visitor &s, const brw_builder &bld,
brw_reg color0, brw_reg color1,
brw_reg src0_alpha, unsigned components,
brw_reg src0_alpha,
unsigned target, unsigned components,
bool null_rt)
{
assert(s.stage == MESA_SHADER_FRAGMENT);
@ -31,6 +32,7 @@ brw_emit_single_fb_write(fs_visitor &s, const brw_builder &bld,
sources[FB_WRITE_LOGICAL_SRC_COLOR0] = color0;
sources[FB_WRITE_LOGICAL_SRC_COLOR1] = color1;
sources[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA] = src0_alpha;
sources[FB_WRITE_LOGICAL_SRC_TARGET] = brw_imm_ud(target);
sources[FB_WRITE_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(components);
sources[FB_WRITE_LOGICAL_SRC_NULL_RT] = brw_imm_ud(null_rt);
sources[FB_WRITE_LOGICAL_SRC_LAST_RT] = brw_imm_ud(false);
@ -72,9 +74,8 @@ brw_do_emit_fb_writes(fs_visitor &s, int nr_color_regions, bool replicate_alpha)
src0_alpha = offset(s.outputs[0], bld, 3);
inst = brw_emit_single_fb_write(s, abld, s.outputs[target],
s.dual_src_output, src0_alpha, 4,
s.dual_src_output, src0_alpha, target, 4,
false);
inst->target = target;
}
if (inst == NULL) {
@ -101,9 +102,8 @@ brw_do_emit_fb_writes(fs_visitor &s, int nr_color_regions, bool replicate_alpha)
const brw_reg tmp = bld.vgrf(BRW_TYPE_UD, 4);
bld.LOAD_PAYLOAD(tmp, srcs, 4, 0);
inst = brw_emit_single_fb_write(s, bld, tmp, reg_undef, reg_undef, 4,
use_null_rt);
inst->target = 0;
inst = brw_emit_single_fb_write(s, bld, tmp, reg_undef, reg_undef,
0, 4, use_null_rt);
}
inst->src[FB_WRITE_LOGICAL_SRC_LAST_RT] = brw_imm_ud(true);

1
src/intel/compiler/brw_eu_defines.h
View file

@ -566,6 +566,7 @@ enum fb_write_logical_srcs {
FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
FB_WRITE_LOGICAL_SRC_TARGET, /* REQUIRED */
FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
FB_WRITE_LOGICAL_SRC_NULL_RT, /* Null RT write */
FB_WRITE_LOGICAL_SRC_LAST_RT, /* Last RT? (bool as UD immediate) */

4
src/intel/compiler/brw_from_nir.cpp
View file

@ -3750,8 +3750,8 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const brw_builder &bld, const b
static brw_inst *
emit_coherent_fb_read(const brw_builder &bld, const brw_reg &dst, unsigned target)
{
brw_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst);
inst->target = target;
brw_inst *inst =
bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst, brw_imm_ud(target));
inst->size_written = 4 * inst->dst.component_size(inst->exec_size);
return inst;

1
src/intel/compiler/brw_inst.h
View file

@ -162,7 +162,6 @@ public:
uint8_t sfid; /**< SFID for SEND instructions */
/** The number of hardware registers used for a message header. */
uint8_t header_size;
uint8_t target; /**< MRT target. */
uint32_t desc; /**< SEND[S] message descriptor immediate */
uint32_t ex_desc; /**< SEND[S] extended message descriptor immediate */

19
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -288,6 +288,8 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
assert(inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
assert(inst->src[FB_WRITE_LOGICAL_SRC_NULL_RT].file == IMM);
assert(inst->src[FB_WRITE_LOGICAL_SRC_LAST_RT].file == IMM);
assert(inst->src[FB_WRITE_LOGICAL_SRC_TARGET].file == IMM);
const intel_device_info *devinfo = bld.shader->devinfo;
const brw_reg color0 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR0];
const brw_reg color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1];
@ -297,10 +299,11 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
brw_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK];
const unsigned components =
inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].ud;
const unsigned target = inst->src[FB_WRITE_LOGICAL_SRC_TARGET].ud;
const bool null_rt = inst->src[FB_WRITE_LOGICAL_SRC_NULL_RT].ud != 0;
const bool last_rt = inst->src[FB_WRITE_LOGICAL_SRC_LAST_RT].ud != 0;
assert(inst->target != 0 || src0_alpha.file == BAD_FILE);
assert(target != 0 || src0_alpha.file == BAD_FILE);
brw_reg sources[15];
int header_size = 2, payload_header_size;
@ -356,8 +359,8 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
}
/* Set the render target index for choosing BLEND_STATE. */
if (inst->target > 0) {
ubld.group(1, 0).MOV(component(header, 2), brw_imm_ud(inst->target));
if (target > 0) {
ubld.group(1, 0).MOV(component(header, 2), brw_imm_ud(target));
}
if (prog_data->uses_kill) {
@ -453,7 +456,7 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
/* XXX - Bit 13 Per-sample PS enable */
inst->desc =
(inst->group / 16) << 11 | /* rt slot group */
brw_fb_write_desc(devinfo, inst->target, msg_ctl, last_rt,
brw_fb_write_desc(devinfo, target, msg_ctl, last_rt,
0 /* coarse_rt_write */);
brw_reg desc = brw_imm_ud(0);
@ -470,7 +473,7 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
uint32_t ex_desc = 0;
if (devinfo->ver >= 20) {
ex_desc = inst->target << 21 |
ex_desc = target << 21 |
null_rt << 20 |
(src0_alpha.file != BAD_FILE) << 15 |
(src_stencil.file != BAD_FILE) << 14 |
@ -480,7 +483,7 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst,
/* Set the "Render Target Index" and "Src0 Alpha Present" fields
* in the extended message descriptor, in lieu of using a header.
*/
ex_desc = inst->target << 12 |
ex_desc = target << 12 |
null_rt << 20 |
(src0_alpha.file != BAD_FILE) << 15;
}
@ -507,6 +510,8 @@ lower_fb_read_logical_send(const brw_builder &bld, brw_inst *inst,
const brw_builder &ubld = bld.exec_all().group(8, 0);
const unsigned length = 2;
const brw_reg header = ubld.vgrf(BRW_TYPE_UD, length);
assert(inst->src[0].file == IMM);
unsigned target = inst->src[0].ud;
assert(devinfo->ver >= 9 && devinfo->ver < 20);
@ -561,7 +566,7 @@ lower_fb_read_logical_send(const brw_builder &bld, brw_inst *inst,
inst->check_tdr = true;
inst->desc =
(inst->group / 16) << 11 | /* rt slot group */
brw_fb_read_desc(devinfo, inst->target,
brw_fb_read_desc(devinfo, target,
0 /* msg_control */, inst->exec_size,
wm_prog_data->persample_dispatch);
}

2
src/intel/compiler/brw_opt_cse.cpp
View file

@ -250,7 +250,6 @@ instructions_match(brw_inst *a, brw_inst *b, bool *negate)
a->size_written == b->size_written &&
a->check_tdr == b->check_tdr &&
a->header_size == b->header_size &&
a->target == b->target &&
a->sources == b->sources &&
a->bits == b->bits &&
operands_match(a, b, negate);
@ -294,7 +293,6 @@ hash_inst(const void *v)
inst->ex_mlen,
inst->sfid,
inst->header_size,
inst->target,
inst->conditional_mod,
inst->predicate,