Commit graph

206154 commits

Author SHA1 Message Date
Brian Paul
64da531799 svga: remove unneeded assignments in svga_set_framebuffer_state()
The util_copy_framebuffer_state() function copies the width, height,
nr_cbufs fields.

Also move a loop variable.

Signed-off-by: Brian Paul <brian.paul@broadcom.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35238>
2025-05-30 16:40:56 +00:00
Brian Paul
dac04694b2 svga: handle NULL surface in svga_surface_needs_propagation()
To avoid null checks at the call sites.

Signed-off-by: Brian Paul <brian.oaul@broadcom.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35238>
2025-05-30 16:40:56 +00:00
Brian Paul
e6058e5ab0 svga: 80-column wrapping and misc code cleanups
No functional changes.

Signed-off-by: Brian Paul <brian.paul@broadcom.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35238>
2025-05-30 16:40:56 +00:00
David Rosca
3bb9905e7f radeonsi/vcn: Use picture fence in JPEG decode
The fence needs to be passed to frontend to make vaSyncSurface work
correctly.

Cc: mesa-stable
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35258>
2025-05-30 16:17:42 +00:00
Guilherme Gallo
e942d1e9e4 bin/ci: crnm: Sanitize n_colums value
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The number of columns should never be less than 1, otherwise we can
break the script such as:

```
Traceback (most recent call last):
  File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 734, in <module>
    main()
  File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 713, in main
    target_job_id, ret, exec_t = monitor_pipeline(
                                 ^^^^^^^^^^^^^^^^^
  File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 221, in monitor_pipeline
    cancel_jobs(project, to_cancel)
  File "/var/home/guilherme/projects/mesa/bin/ci/ci_run_n_monitor.py", line 400, in cancel_jobs
    print_formatted_list(cancelled_jobs, indentation=8)
  File "/var/home/guilherme/projects/mesa/bin/ci/gitlab_gql.py", line 373, in print_formatted_list
    step = (len(elements) // n_columns) + 1
            ~~~~~~~~~~~~~~^^~~~~~~~~~~
ZeroDivisionError: integer division or modulo by zero
```

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35250>
2025-05-30 13:15:37 +00:00
Yao Zi
b1d81a7df1 radeonsi: Fix violation of aliasing rules in radeon_ws_bo_reference
Applications using Mesa built with LLVM 20.1.4 fail to start with
strange segmentfaults/bus errors when radeonsi driver is used. The last
piece of stacktrace looks like

  - pipe_reference_described
  - pipe_reference
  - radeon_bo_reference
  - radeon_ws_bo_reference
  - radeon_lookup_or_add_real_buffer

Coredump shows the pointer dst passed to pipe_reference_described() is
either unaligned or even invalid, which is the reason of crashing. The
crash goes away when Mesa is built without optimization.

Looking through the related functions, it's found that
radeon_ws_bo_reference() contains unsafe type cast from radeon_bo to
pb_buffer_lean: though the former's first field is just the later, this
violates strict aliasing rules as pb_buffer_lean isn't compatible with
radeon_bo. Such violation ultimately results in miscompilation.

Let's take the address of pb_buffer_lean field, avoiding the unsafe
cast. It's still required to cast pb_buffer_lean back to radeon_bo since
radeon_bo_reference may update the pointer, which is safe as radeon_bo
contains a pb_buffer_lean member and C language permits access members
through a pointer in type of the container.

Fixes: 6d913a2bcc ("r300,r600,radeonsi: switch to pb_buffer_lean")
Link: https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Aliasing-Type-Rules.html
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35249>
2025-05-30 12:48:18 +00:00
Juan A. Suarez Romero
f340990fcb v3dv: don't use deprecated NIR_PASS_V macro
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Check more details at
https://gitlab.freedesktop.org/mesa/mesa/-/issues/10409.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35127>
2025-05-30 14:24:24 +02:00
Juan A. Suarez Romero
5505bb6c6d v3d/compiler: don't use deprecated NIR_PASS_V macro
We still keep it for the case of nir_scheduling, as this pass requires
to be adapted to return the progress as well as update the metadata.

Check more details at
https://gitlab.freedesktop.org/mesa/mesa/-/issues/10409.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35127>
2025-05-30 14:24:24 +02:00
Juan A. Suarez Romero
62ba0d7bf8 vc4: don't use deprecated NIR_PASS_V macro
Check more details at
https://gitlab.freedesktop.org/mesa/mesa/-/issues/10409.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35127>
2025-05-30 14:24:24 +02:00
Juan A. Suarez Romero
b5706ef70a vc4: return progress on custom nir lowering
Report if the vc4 specific NIR lowering did any progress.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35127>
2025-05-30 14:24:24 +02:00
David Rosca
a9a54632af frontends/va: Fix H264 top/bottom is reference flags
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All pics in the ReferenceFrames array should be references,
so there is no need to require the SHORT_TERM_REFERENCE flag
to actually treat them as references.
This fixes decoding with apps that doesn't set this flag,
eg. NoMachine remote desktop viewer (nxplayer).

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13229
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35186>
2025-05-30 08:54:31 +00:00
David Rosca
8f4e251c98 radeonsi/vcn: Support disabling HEVC dependent slice segments
With older FW this needs to be always enabled, but it can now be
disabled when using the new separate header instructions for
dependent_slice_segment_flag and slice_segment_address.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35072>
2025-05-30 08:29:53 +00:00
David Rosca
09a1429a00 radeonsi/vcn: Remove carrizo workaround
Carrizo has UVD so this can never be true.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35072>
2025-05-30 08:29:53 +00:00
David Rosca
f17ea8e901 radeonsi/vcn: Get rid of not_referenced
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35072>
2025-05-30 08:29:52 +00:00
Jesse Natalie
47f4d3e701 d3d12: Handle a null threaded context
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When GALLIUM_THREAD=0, the threaded context doesn't get created and
the following lines would fault.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35248>
2025-05-30 02:19:26 +00:00
Jesse Natalie
0c0f6c6df1 d3d12: Handle sampler view creation on B8G8R8X8
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35142>
2025-05-30 01:24:10 +00:00
Jesse Natalie
f5781553f6 winsys/d3d12: Support no-alpha formats through the DXGI swapchain path
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35142>
2025-05-30 01:24:10 +00:00
Eric R. Smith
548f652d10 panfrost, panvk: spread hierarchy mask bits out when max_levels < 8
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We create hierarchy masks based on the number of levels available,
creating a bitmask with `max_levels` bits set. Originally these bits
all came together. Modify this to spread the bits out, which improves
performance on chips like the G31 with only 2 levels of hierarchy.

Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34744>
2025-05-29 21:50:54 +00:00
Eric R. Smith
13b35a3c9c panfrost, panvk: fix G31 use of SHADER_MODE_EARLY_ZS_ALWAYS
PRE_POST_FRAME_SHADER_MODE_EARLY_ZS_ALWAYS was introduced in
architecture version 7.2, not 7.0 as we assumed. Using it on
G31 (a 7.0 device) caused some CTS failures.

Cc: mesa-stable
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34744>
2025-05-29 21:50:52 +00:00
Faith Ekstrand
2e85076b1d nak: Set cache ops on surface load/store ops
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2025-05-29 21:02:37 +00:00
Faith Ekstrand
ad98b76a14 nak: Set cache ops on global memory access on Kepler
For now we leave shared and local alone on SM32 (there are no such
controls on SM20).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35217>
2025-05-29 21:02:37 +00:00
Faith Ekstrand
a7760e4bd8 nak: Set MemOrder::Constant for CAN_REORDER image loads on all hardware
On Turing and Volta, it will safely degrade suld.weak.  On Maxwell and
Pascal, it will degrade to suld.cta.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35217>
2025-05-29 21:02:37 +00:00
Faith Ekstrand
d3b9752ee6 nak/sm50: Use MemScope::CTA for constant image loads
Using MemScope::System synchronizes with everything, which is exactly
what we don't want for constant loads.  This is currently a no-op
because we aren't using MemScope::Constant pre-Ampere yet.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35217>
2025-05-29 21:02:37 +00:00
Faith Ekstrand
6ea0e91c99 nak: Handle suld.constant on Turing and Volta in legalization
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35217>
2025-05-29 21:02:37 +00:00
Lionel Landwerlin
f0e18c475b intel: remove GRL/intel-clc
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35227>
2025-05-29 20:17:13 +00:00
Mike Blumenkrantz
44bff7eb05 zink: fix queue transition check in check_for_layout_update()
this only applies if the resource has active binds, otherwise it triggers crashes

Fixes: 18d206d67c ("zink: Check queue families when binding image resources")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35234>
2025-05-29 15:25:04 -04:00
Mel Henning
6c68c2c3ba nak/spill_values: Follow phis from src to dest
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ssa_state_out has the predecessor's SSAValue, so we need look for it in
the phi_src map.

Totals:
CodeSize: 4545122720 -> 4534830176 (-0.23%); split: -0.23%, +0.00%
Number of GPRs: 10963889 -> 10963693 (-0.00%); split: -0.00%, +0.00%
SLM Size: 1855380 -> 1649308 (-11.11%); split: -11.11%, +0.01%
Static cycle count: 1104322907 -> 1093035821 (-1.02%); split: -1.02%, +0.00%
Spills to memory: 480689 -> 139107 (-71.06%)
Fills from memory: 480689 -> 139107 (-71.06%)
Spills to reg: 458804 -> 242139 (-47.22%); split: -47.23%, +0.01%
Fills from reg: 303068 -> 222030 (-26.74%); split: -26.75%, +0.01%
Max warps/SM: 7245516 -> 7245580 (+0.00%)

Totals from 9899 (5.04% of 196502) affected shaders:
CodeSize: 1056727952 -> 1046435408 (-0.97%); split: -0.98%, +0.00%
Number of GPRs: 1666652 -> 1666456 (-0.01%); split: -0.01%, +0.00%
SLM Size: 1107988 -> 901916 (-18.60%); split: -18.61%, +0.01%
Static cycle count: 254942337 -> 243655251 (-4.43%); split: -4.43%, +0.01%
Spills to memory: 480689 -> 139107 (-71.06%)
Fills from memory: 480689 -> 139107 (-71.06%)
Spills to reg: 367784 -> 151119 (-58.91%); split: -58.92%, +0.01%
Fills from reg: 222209 -> 141171 (-36.47%); split: -36.49%, +0.02%
Max warps/SM: 119188 -> 119252 (+0.05%)

Fixes: bcad2add47 ("nak: Add a spilling pass")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35143>
2025-05-29 18:30:40 +00:00
Mel Henning
0e5880ebe4 nvk: Call ensure_slm for nvk_cmd_dispatch_shader
Internal shaders can also use slm, so we need to allocate it correctly.

This fixes
dEQP-VK.dgc.ext.compute.misc.max_pc_range_256_full_preprocess_with_execution_set
with NAK_DEBUG=spill

Fixes: 105bdf2e36 ("nvk: Add a helper for dispatching compute shaders")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35143>
2025-05-29 18:30:40 +00:00
Mike Blumenkrantz
d8d913c341 zink: also check for host-visible on staging uploads
this has strange mechanics on lavapipe

Fixes: e63acdd2b7 ("zink: force cached mem for streaming uploads")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35239>
2025-05-29 13:18:23 -04:00
Faith Ekstrand
cfeda2d8ae nvk: Disallow GetMemoryFdProperties with OPAQUE_FD_BIT
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35213>
2025-05-29 11:53:27 -04:00
Faith Ekstrand
601cf33c44 nvk: Only allow importing mappable dma-bufs to HOST_VISIBLE types
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35213>
2025-05-29 11:53:27 -04:00
Faith Ekstrand
77eba0980b nvk: Don't assert memory placement on import
Instead, we assert that the non-placement flags match, which is
currently CAN_MAP and SHARED.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35213>
2025-05-29 11:53:27 -04:00
Faith Ekstrand
bf82c94751 nvk/nvkmd: Add a force_mem_to_gart() helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35213>
2025-05-29 11:53:27 -04:00
Mike Blumenkrantz
05f8b59c90 gallium: delete union pipe_surface_desc
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this is no longer used

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35168>
2025-05-29 13:07:02 +00:00
Mike Blumenkrantz
ca65f2cf1c gallium: delete pipe_surface::writable
no longer used

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35168>
2025-05-29 13:07:02 +00:00
Samuel Pitoiset
9692ef41a3 aco: implement bitfield_extract for 8-bit/16-bit
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35199>
2025-05-29 12:24:59 +00:00
Daniel Stone
80e19e7b1e ci: Bump v6.14 kernel for updated Panthor scheduler
Apply a newer version of the Panthor scheduling timeout fix from the
list.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35230>
2025-05-29 12:05:06 +01:00
Karmjit Mahil
688d8217a5 tu,freedreno: Add pkt_field_{get,set} helper macro
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It's very common needing to extract or overwrite a certain field
in an already packed register value, so add macros to do that
instead of manually doing that each time.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35088>
2025-05-29 10:54:28 +01:00
Danylo Piliaiev
398f14ca3d freedreno: Use fast variants of {BC4/BC5}_SNORM formats
Hardware has two types of BC4 and BC5: fast and not.
The exact perf difference is not tested, but these distinct formats
could be seen in the public docs:
Qualcomm Adreno GPU > Spec Sheet -> Texture format
https://docs.qualcomm.com/bundle/publicresource/topics/80-78185-2/spec_sheets.html?product=1601111740035277#panel-0-0-1

Found when scanning prop driver's cmdstream seeing unknown format.

Passes:
dEQP-VK.*bc4*
dEQP-VK.*bc5*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33945>
2025-05-29 09:01:17 +00:00
Eric Engestrom
5a5b00cfca ci: drop unneeded printing of pass/fail alongside the exit_code
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35214>
2025-05-29 07:29:25 +00:00
Samuel Pitoiset
fe2c93a788 ac/nir: enable 64-bit lowering for bitfield_extract
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35187>
2025-05-29 08:45:41 +02:00
Samuel Pitoiset
cecf6675be nir/lower_int64: add bitfield_extract lowering
This will be used by RADV for ACO/LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35187>
2025-05-29 08:45:40 +02:00
Olivia Lee
104ea2e4cf panfrost: legalize afbc before zs and rt clears
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In panfrost_clear_depth_stencil and panfrost_clear_render_target, we
start the blit context before binding the clear targets. If we don't
legalize AFBC beforehand, we get a recursive blit crash. panfrost_clear
does not need this because the resource should already be legalized in
panfrost_batch_add_surface.

Fixes the following piglit tests with pan_force_afbc_packing:
 - spec@arb_clear_texture@arb_clear_texture-base-formats
 - spec@arb_clear_texture@arb_clear_texture-simple
 - spec@arb_clear_texture@arb_clear_texture-sized-formats

Fixes: 17a62ff993 ("panfrost: legalize afbc before blitting")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34992>
2025-05-29 01:50:31 +00:00
Olivia Lee
bed54fa402 panfrost: fix assertion failure compiling image conversion shaders
In 59a3e12039, we changed the UBO->push optimization in panfrost to
only push UBOs that are available in a CPU buffer. We require
first_ubo_is_default_ubo, to ensure that UBO0 will be a user buffer. We
weren't setting this flag for the image conversion shaders, so got an
assertion failure compiling them. This can be triggered by the
panvk_force_afbc_packing driconf option.

The conversion shader info UBO isn't exactly a "default" UBO in the
sense of being lowered from uniforms, but it is a user buffer, so
setting the flag should be fine.

Fixes: 59a3e12039 ("panfrost: do not push "true" UBOs")
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34992>
2025-05-29 01:50:31 +00:00
Yiwei Zhang
749265da0d vulkan/wsi: split cmd record for img2buf blit and img2img blit
There's no behavior change, but to prepare for the next img2buf blit
improvement, except adding asserts to make clear of the existing blit
code paths.

v2: use switch with unreachable default per @gfxstrand has suggested

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35220>
2025-05-29 01:20:27 +00:00
Yiwei Zhang
2af2314fb2 vulkan/wsi: include missing barrier for transferring to blit dst image
Fixes: 2975a7f453 ("vulkan/wsi: Add support for image -> image blits")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35220>
2025-05-29 01:20:27 +00:00
Pohsiang (John) Hsu
79bc373b1e mediafoundation: move readme.md to docs folder
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35219>
2025-05-29 01:03:34 +00:00
Pohsiang (John) Hsu
0107d94632 mediafoundation: add mechanism to disable async and h.264 unwrapped POC (commented out for now) according to gpu/version
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35219>
2025-05-29 01:03:34 +00:00
Pohsiang (John) Hsu
061085708a mediafoundation: on use LTR, synchronize the active ltr bitmap to the one passed in
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35219>
2025-05-29 01:03:34 +00:00
Pohsiang (John) Hsu
22d84522ed mediafoundation: get device vendor id, device id, and driver version
Reviewed-by: Yubo Xie <yuboxie@microsoft.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35219>
2025-05-29 01:03:34 +00:00