Commit graph

12621 commits

Author SHA1 Message Date
Deborah Brouwer
18f15da94d ci/intel: add i915/MTL firmware to rootfs
Add Meteor Lake firmware directly to rootfs since it is not available
from debian package.

Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30770>
2024-08-28 04:31:10 +00:00
Caio Oliveira
695f5314d6 intel/brw: Simplify fs_inst annotation
When INTEL_DEBUG=ann is also set, the disassembler would annotate the
output with either a string or the string verison of a NIR instruction.
This was done by keeping two pointers (but only using one at a time).

Change the code to print the instruction into a string instead of
keeping it pointer around (peg the string to the shader).  That way,
only one pointer is needed for annotations.  Because that serialization
is not free, only do that when the environment variable is set.

Since we are here, move the annotation string field to the end, moving
it to the least commonly used cacheline.  Further packing might allow
the entire fs_inst to fit in two cachelines.

For release builds, don't even add the debug annotation to the struct.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30822>
2024-08-28 03:59:50 +00:00
Caio Oliveira
ec15cdfa2a intel/brw: Pack brw_reg struct
The alignment required for the second union (has 64-bit size) causes
a hole between the first and second union.  Move the remaining data
there.

In 64-bit build, shrinks brw_reg from 24 bytes to 16 bytes.  And by
consequence, shirnks fs_inst from 200 bytes to 160 bytes, making it
use one less cacheline.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30822>
2024-08-28 03:59:50 +00:00
Iván Briano
2261b298d1 anv: fix adding to wa_addr
Fixes: 6336e0fe7f ("anv: order data in wa_bo to leave wa_addr last")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30881>
2024-08-27 18:10:58 -07:00
Sagar Ghuge
063715ed45 anv: Reduce clear color state alignment to 64B
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26793>
2024-08-27 21:13:30 +00:00
Lionel Landwerlin
e97b968aeb brw: add a comment what Gfx12.5 URB fences
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30849>
2024-08-27 13:38:14 +00:00
Lionel Landwerlin
93fba40389 brw: switch mesh/task URB fence prior to EOT to GPU
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30849>
2024-08-27 13:38:14 +00:00
Sergi Blanch Torne
1b51e24b0a New testing jobs intel-adl-skqp
Introduce skqp testing on ADL generation. Only one job on the pre-merge, and
no fraction needed, so not required to set up a job for nightly runs.
Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
2024-08-27 12:49:28 +02:00
Sergi Blanch Torne
c653e98748 New testing jobs anv-adl-angle{,-full}
Introduce testing coverage for Angle in ANV driver on ADL generation. One job
in the pre-merge fraction, and another for the full coverage on the nightly
runs. Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
2024-08-27 12:49:24 +02:00
Sergi Blanch Torne
6c9138f86a New testing jobs anv-adl{,-full}
Introduce testing coverage for ANV driver on ADL generation. Sharded in 4 jobs
the pre-merge fraction, and with 5 jobs the full coverage on the nightly runs.
Introduced the initial expectation files with fails, flakes, and skips.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
2024-08-27 12:49:21 +02:00
Sergi Blanch Torne
fce5e77604 New DUT for Alder Lake
Introduce a new runner tag from a hidden job for ADL (Alder Lake Intel
generation), known as brya.

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26831>
2024-08-27 12:49:16 +02:00
Kenneth Graunke
437bda3013 intel/brw: Get rid of the lsc_msg_desc_wcmask helper
The LOAD/STORE opcodes take a vector size, while the LOAD/STORE_CMASK
opcodes take a channel mask.  The two are mutually exclusive.  So we
can just have the lsc_msg_desc() helper take one or the other in the
same parameter.  This more closely matches the actual descriptor.

We couldn't do this until the previous commit, since we were previously
relying on the lsc_msg_desc() function to calculate a cmask out of the
number of vector components.  But now we don't need it to do that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30632>
2024-08-27 09:25:59 +00:00
Kenneth Graunke
55f193a105 intel/brw: Switch from LSC CMASK opcodes to regular LOAD/STORE
The LOAD/STORE opcodes take a vector size (number of components), while
the LOAD/STORE_CMASK opcodes take a channel mask.  For some reason, we
were passing a number of channels to lsc_msg_desc(), then using it to
construct a channel mask with all channels enabled, and always using the
CMASK message variants.

Considering we don't actually want to mask off any channels, we should
probably just use the regular LOAD/STORE opcodes, as they're more
flexible anyway.

One exception is that typed messages on Xe2 apparently only support
LOAD_CMASK/STORE_CMASK and not regular LOAD/STORE.  So we keep using
those there.  (Thanks to Sagar Ghuge for catching this!)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30632>
2024-08-27 09:25:58 +00:00
Sviatoslav Peleshko
7e52b67801 anv: Add full subgroups WA for the shaders with barriers in Breaking Limit
When barriers are used in invalid shaders with non-uniform control flow
we might get a hang. Forcing 32-wide group can help by making it more
probable that barrier instruction is executed by at least one channel
in each thread, and thus hang will be avoided. This shouldn't affect
Xe2+, where active-thread-only barriers are used anyway.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11497
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
2024-08-27 08:26:08 +00:00
Sviatoslav Peleshko
1904fe1186 anv: Release correct BO in anv_cmd_buffer_set_ray_query_buffer
If p_atomic_cmpxchg doesn't set the ray_query_shadow_bos[bucket] to new_bo
allocated by this thread, it returns the bucket BO allocated by the other
thread and we use it. But due to a mistake, we also release that BO, not
the candidate just allocated by this thread and never used again.

Fixes: 5d3e4193 ("anv: enable ray queries")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
2024-08-27 08:26:08 +00:00
Sviatoslav Peleshko
09122e2be0 brw,elk: Fix opening flags on dumping shader binaries
Truncation is needed for overwriting correctly in cases when old file is
bigger than the one we want to dump (e.g. when the old one was edited
inplace). Also, creation permissions are way too broad.

Fixes: 4f41c44d ("intel/compiler: Add variable to dump binaries of all compiled shaders")
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
2024-08-27 08:26:08 +00:00
Sviatoslav Peleshko
442cc7996e anv: Assert ray query BO actually exists
The crash will happen if the client tries to use ray queries without
enabling the KHR_ray_query extension. Add an assert to be able to catch
this sooner.

Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30581>
2024-08-27 08:26:08 +00:00
Nanley Chery
4a8f3181ba intel: Support any depth fast-clear value on Xe2
Remove the restriction that a depth fast-clear must have a clear value
which matches an image-dependent heuristic.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30767>
2024-08-27 06:15:36 +00:00
Nanley Chery
4a9e45061a anv: Add and use anv_image_hiz_clear_value()
The benchmarks we're tracking tend to prefer clearing depth buffers to
0.0f when the depth buffers are part of images with multiple aspects.
Otherwise, they tend to prefer clearing depth buffers to 1.0f.

Replace the ANV_HZ_FC_VAL constant with a function which implements this
heuristic.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30767>
2024-08-27 06:15:36 +00:00
Nanley Chery
9fd79dc49e anv: Pass the VkClearDepthStencilValue for clears
Xe2 can easily support fast-clearing depth buffers to multiple clear
values. Instead of assuming a hard-coded value in various parts of the
driver, pass the clear value down the expected paths.

For consistency, also adjust the slow depth clear function to have a
matching parameter.

Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30767>
2024-08-27 06:15:36 +00:00
Paulo Zanoni
f3c7e14f09 isl: don't assert(num_elements > (1ull << 27))
Some games such as Marvel's Spider-Man Remastered and Assassin's
Creed: Valhalla don't work in debug mode because they hit this
assertion. In Release mode, they appear to work (although in some
platforms there may be visual corruption or GPU hangs). There's
nothing we can do about this error (see below), so in this patch we
replace the assertion with an error message, because it allows us to
(i) test the rest of the game in debug mode so we may catch other
issues; and (ii) warn users of release mode that the issue is
happening.

The unsupported num_elements comes from vkGetDescriptorEXT() and
appears to be violating VUID-VkDescriptorGetInfoEXT-type-09427. This
function cannot return errors, but we can disable
VK_EXT_descriptor_buffer.

If we do disable the extension, then vkCreateBufferView() will start
triggering the assertion, and we can see that
VkBufferViewCreateInfo-range-00930 is being violated. If we change Anv
to return errors on these vkCreateBufferView() cases, then the games
won't work at all.

I reported this to vkd3d-proton, but according to the vkd3d-proton
developer Philip Rebohle:

 "There's also the problematic case of games using typed descriptors
  but passing non-typed buffer descriptors, which is an extremely
  common app bug that works on all D3D12 drivers that we need to work
  around by creating typed views. If that's what's happening here then
  the best we can do is to just not create the typed view and have the
  game be broken entirely, or create a smaller view and most likely
  still completely break the game, but at least that way it wouldn't
  trigger Vulkan validation. Emulating larger views via multiple
  smaller views is not possible for us."

 "Confirmed that it's the app itself creating these views."

 "D3D12 does not have runtime validation for this or any sort of query
  for the app, so we really can't do much here."

Link: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9963
Link: https://github.com/HansKristian-Work/vkd3d-proton/issues/2071
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30775>
2024-08-27 05:47:50 +00:00
Lionel Landwerlin
6336e0fe7f anv: order data in wa_bo to leave wa_addr last
We want to make sure the workaround_address is the last item in the BO
so that we don't have to care about the size of the writes going
there, we'll be sure they won't overwrite other items in that BO.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7b9400b7f7 ("intel/blorp: Don't use clear color conversion on gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11775
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30844>
2024-08-27 00:51:03 +00:00
Lionel Landwerlin
d8ec8acede anv: always use workaround_address, not workaround_bo
The workaround BO has some debug information at the beginning. The
workaround address is placed after that.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30844>
2024-08-27 00:51:03 +00:00
Nanley Chery
9b98cebe9a intel: Drop BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
All drivers update the clear color themselves. So, drop the
functionality from BLORP as well as the flag controlling it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30824>
2024-08-26 23:57:12 +00:00
Nanley Chery
721d0c3e77 anv,hasvk: Always use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
Store the clear color from within the drivers, rather than from BLORP.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30824>
2024-08-26 23:57:11 +00:00
Nanley Chery
5fd42500cf anv,hasvk: Add and use set_image_clear_color()
We're going to be storing clear colors from the drivers rather than
BLORP. Add a function for this purpose.

For now, the first use replaces init_fast_clear_color(). One change in
behavior is that the clear color initialization is now done without
write-checking on gfx12. This actually matches what anv does to other
writes to the image's fast-clear tracking state. We can fix this later
if and when we address the larger issue.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30824>
2024-08-26 23:57:11 +00:00
Lionel Landwerlin
1f9c40a8d1 anv: explicitly disable BT pool allocations at device init
The default state doesn't seem well defined (or kernel driver bug
maybe?). Let's just set it to disabled on platforms where we're not
using it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Found-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30841>
2024-08-26 10:34:31 +00:00
Caio Oliveira
31dfb04fd3 intel/brw: Remove long register file names
The long names were originally meant to map to the HW encoding but
nowadays the actual encoding values depend on gfx version, whether
instruction is 3src, etc.

Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
6bdf2de4d2 intel/brw: Remove unused ARF values and helpers
These were used by old Gfx versions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
72b687abb4 intel/brw: Make BAD_FILE the zero value for brw_reg_file
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
e8f921678a intel/brw: Explicitly map brw_reg_file into hardware values
For now this is a no-op, but will be useful when changing the enum
to values that don't match the hardware.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
e7179232c9 intel/brw: Move encoding of Gfx11 3-src inside the inst helpers
Create specific helper for register file encoding and handle it there.
Use ad-hoc structs to let the macro take optional named arguments.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
d31c8bfb6f intel/brw: Remove more uses of variable length arrays
In these cases there's a clear bound we can use.  In C++ this is a
compiler extension and not compatible with zero initializing a
regular struct -- which will happen in a later change.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
86c20e2910 intel/brw: Use a helper for common VEC pattern
In the helper, instead of using the Variable Length Array, use a
fixed size array to NIR_MAX_VEC_COMPONENTS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:14 +00:00
Caio Oliveira
abc535a3b4 intel/brw: Remove unused variable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30704>
2024-08-25 22:08:13 +00:00
Nanley Chery
23658920d1 anv,iris: Skip tex invalidate for clear conversion
The hardware's clear color conversion feature requires invalidating the
texture cache for every fast clear. We're no longer using the hardware
feature, so we longer need the invalidation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30646>
2024-08-23 15:28:34 +00:00
Nanley Chery
7b9400b7f7 intel/blorp: Don't use clear color conversion on gfx12
Instead of using the clear color conversion feature by the hardware, use
software to write out the converted clear color pixel.

When testing a patch which moves a state cache invalidate to occur after
fast clears instead of before, this prevents the following failures on
tgl/zink:

* piglit.spec.arb_texture_cube_map_array.arb_texture_cube_map_array-cubemap
* piglit.spec.ext_framebuffer_object.fbo-generatemipmap-formats

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30646>
2024-08-23 15:28:34 +00:00
Nanley Chery
b404ca0eb0 intel: Don't use HW clear color conversion on gfx11
The hardware's clear color conversion feature unfortunately requires
invalidating the texture cache for every fast clear. To avoid the
performance penalty that comes with the invalidation, avoid using the
hardware feature and write out the converted clear color pixel
ourselves.

When testing a patch which moves a state cache invalidate to occur after
fast clears instead of before, this prevents the following failures on
icl/zink:

* piglit.fast_color_clear.fcc-read-after-clear sample tex
* piglit.spec.arb_clear_texture.arb_clear_texture-cube

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30646>
2024-08-23 15:28:34 +00:00
Nanley Chery
dfcd93d12f intel/isl: Fix packing of SINT formats
Prevents the next patch from failing many multisampled, signed integer
rendering tests. For example:

 dEQP-VK.renderpass2.suballocation.multisample_resolve.r8_sint.samples_4

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30646>
2024-08-23 15:28:34 +00:00
Lionel Landwerlin
778cb59086 anv: optimize STATE_BYTE_STRIDE emission
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30803>
2024-08-23 10:52:19 +00:00
Lionel Landwerlin
195c5b68ba anv: don't miss workaround for indirect draws
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30803>
2024-08-23 10:52:19 +00:00
Lionel Landwerlin
f25b500af4 anv: move conditional render predicate after gfx_flush_state
Following up on f8c0a99d52 ("anv: emit conditional after gfx state
flushing"), this should have been applied everywhere.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0147908a89 ("anv: predicate emission of STATE_BASE_ADDRESS")
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30803>
2024-08-23 10:52:19 +00:00
Tapani Pälli
5bf6602d23 anv: check if RT writes are happening for HasWriteableRT
Fixes: eebb6cd236 ("anv: stop using 3DSTATE_WM::ForceThreadDispatchEnable")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11749
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30785>
2024-08-23 06:28:00 +00:00
Lionel Landwerlin
a88898a28f anv: optimize CLIP::MaximumVPIndex setting
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11746
Fixes: 982106e676 ("anv: only set 3DSTATE_CLIP::MaximumVPIndex once")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30762>
2024-08-23 05:45:03 +00:00
Kenneth Graunke
b97e10208c intel/brw: Add a file parameter to idom_tree::dump()
The other dump methods in this file also take a file parameter,
defaulting to stderr.  Dumping dot files to stdout is probably not
what anybody really wanted.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30530>
2024-08-22 22:54:45 +00:00
Kenneth Graunke
bb4f05005e intel/brw: Print blocks in brw_print_instructions_to_file()
Useful when examining the control flow graph.  For some reason,
we printed this for the final assembly but not the IR.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30530>
2024-08-22 22:54:45 +00:00
Kenneth Graunke
2d73e42333 intel/brw: Fix OOB reads when printing instructions post-reg-alloc
Post-register allocation, but before brw_fs_lower_vgrfs_to_fixed_grfs,
we have registers with the VGRF file but they are actually fixed GRFs.

brw_print_instructions_to_file() was seeing VGRFs and trying to access
their size, but using bogus register numbers that could be out-of-bound.

Detect when we're post-RA and avoid doing this.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30530>
2024-08-22 22:54:45 +00:00
Lionel Landwerlin
d9406658ed brw: remove unused prog_data field
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:40 +00:00
Lionel Landwerlin
3769b58272 anv: move lowering of descriptor intrinsics to apply_layout
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:40 +00:00
Lionel Landwerlin
45117c0ed5 anv: simplify loading driver internal constants
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
2024-08-22 19:44:39 +00:00