Caio Oliveira ec15cdfa2a intel/brw: Pack brw_reg struct ... The alignment required for the second union (has 64-bit size) causes a hole between the first and second union. Move the remaining data there. In 64-bit build, shrinks brw_reg from 24 bytes to 16 bytes. And by consequence, shirnks fs_inst from 200 bytes to 160 bytes, making it use one less cacheline. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30822>		2024-08-28 03:59:50 +00:00
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blorp	intel: Support any depth fast-clear value on Xe2	2024-08-27 06:15:36 +00:00
ci	New testing jobs intel-adl-skqp	2024-08-27 12:49:28 +02:00
common	intel: Remove INTEL_ENGINE_CLASS_COMPUTE and INTEL_ENGINE_CLASS_COPY parameters	2024-08-13 21:15:31 +00:00
compiler	intel/brw: Pack brw_reg struct	2024-08-28 03:59:50 +00:00
decoder	intel/decoder: Handle HCP_PAK_INSERT_OBJECT	2024-08-02 07:15:59 +00:00
dev	intel/dev: update mesa_defs.json from workaround database	2024-08-14 11:20:40 +00:00
ds	anv/hasvk: add indirect tracepoint arguments	2024-08-03 16:03:04 +03:00
executor	intel/brw: Use %td format for pointer difference	2024-08-14 17:28:41 -07:00
genxml	anv,iris: prefix the argument format with XI for a upcoming refactor	2024-08-20 09:41:51 +00:00
isl	isl: don't assert(num_elements > (1ull << 27))	2024-08-27 05:47:50 +00:00
nullhw-layer	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
perf	intel/dev: Support new topology type with SIMD16 EUs	2024-08-05 07:01:47 -07:00
shaders	meson: use glslang --depfile argument when possible	2024-05-20 17:34:17 +00:00
tools	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
vulkan	anv: fix adding to wa_addr	2024-08-27 18:10:58 -07:00
vulkan_hasvk	intel: Drop BLORP_BATCH_NO_UPDATE_CLEAR_COLOR	2024-08-26 23:57:12 +00:00
meson.build	intel: Add executor tool	2024-08-14 03:03:46 +00:00