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anv: simplify loading driver internal constants

Browse source 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30713>
This commit is contained in:
Lionel Landwerlin 2024-05-12 15:21:36 +03:00 • committed by Marge Bot
parent 7a55a930f6
commit 45117c0ed5
5 changed files with 47 additions and 59 deletions
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21
src/intel/vulkan/anv_nir.h
View file

@ -31,6 +31,27 @@
extern "C" {
#endif
#define anv_drv_const_offset(field) \
(offsetof(struct anv_push_constants, field))
#define anv_drv_const_size(field) \
(sizeof(((struct anv_push_constants *)0)->field))
#define anv_load_driver_uniform(b, components, field) \
nir_load_push_constant(b, components, \
anv_drv_const_size(field) * 8, \
nir_imm_int(b, 0), \
.base = anv_drv_const_offset(field), \
.range = components * anv_drv_const_size(field))
#define anv_load_driver_uniform_indexed(b, components, field, idx) \
nir_load_push_constant(b, components, \
anv_drv_const_size(field[0]) * 8, \
nir_imul_imm(b, idx, \
anv_drv_const_size(field[0])), \
.base = anv_drv_const_offset(field), \
.range = anv_drv_const_size(field))
/* This map is represent a mapping where the key is the NIR
* nir_intrinsic_resource_intel::block index. It allows mapping bindless UBOs
* accesses to descriptor entry.

33
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
View file

@ -37,8 +37,6 @@
#define MAX_SAMPLER_TABLE_SIZE 128
#define BINDLESS_OFFSET 255
#define sizeof_field(type, field) sizeof(((type *)0)->field)
enum binding_property {
BINDING_PROPERTY_NORMAL = BITFIELD_BIT(0),
BINDING_PROPERTY_PUSHABLE = BITFIELD_BIT(1),
@ -871,12 +869,7 @@ build_surface_index_for_binding(nir_builder *b,
surface_index =
build_load_descriptor_mem(b, desc_addr, 0, 1, 32, state);
} else {
set_offset =
nir_load_push_constant(b, 1, 32, nir_imm_int(b, 0),
.base = offsetof(struct anv_push_constants,
desc_surface_offsets[set]),
.range = sizeof_field(struct anv_push_constants,
desc_surface_offsets[set]));
set_offset = anv_load_driver_uniform(b, 1, desc_surface_offsets[set]);
/* With bindless indexes are offsets in the descriptor buffer */
surface_index =
@ -966,12 +959,7 @@ build_sampler_handle_for_binding(nir_builder *b,
sampler_index = nir_channel(b, desc_data, 1);
} else {
set_offset =
nir_load_push_constant(b, 1, 32, nir_imm_int(b, 0),
.base = offsetof(struct anv_push_constants,
desc_sampler_offsets[set]),
.range = sizeof_field(struct anv_push_constants,
desc_sampler_offsets[set]));
set_offset = anv_load_driver_uniform(b, 1, desc_sampler_offsets[set]);
uint32_t base_offset = descriptor_offset;
@ -1029,9 +1017,7 @@ build_buffer_dynamic_offset_for_res_index(nir_builder *b,
nir_def *dyn_offset_idx = nir_iadd(b, dyn_offset_base, array_index);
nir_def *dyn_load =
nir_load_push_constant(b, 1, 32, nir_imul_imm(b, dyn_offset_idx, 4),
.base = offsetof(struct anv_push_constants, dynamic_offsets),
.range = sizeof_field(struct anv_push_constants, dynamic_offsets));
anv_load_driver_uniform_indexed(b, 1, dynamic_offsets, dyn_offset_idx);
return nir_bcsel(b, nir_ieq_imm(b, dyn_offset_base, 0xff),
nir_imm_int(b, 0), dyn_load);
@ -1077,9 +1063,7 @@ build_indirect_buffer_addr_for_res_index(nir_builder *b,
nir_iadd(b, res.dyn_offset_base, res.array_index);
nir_def *dyn_load =
nir_load_push_constant(b, 1, 32, nir_imul_imm(b, dyn_offset_idx, 4),
.base = offsetof(struct anv_push_constants, dynamic_offsets),
.range = MAX_DYNAMIC_BUFFERS * 4);
anv_load_driver_uniform_indexed(b, 1, dynamic_offsets, dyn_offset_idx);
nir_def *dynamic_offset =
nir_bcsel(b, nir_ieq_imm(b, res.dyn_offset_base, 0xff),
@ -1730,9 +1714,7 @@ lower_base_workgroup_id(nir_builder *b, nir_intrinsic_instr *intrin,
b->cursor = nir_instr_remove(&intrin->instr);
nir_def *base_workgroup_id =
nir_load_push_constant(b, 3, 32, nir_imm_int(b, 0),
.base = offsetof(struct anv_push_constants, cs.base_work_group_id),
.range = sizeof_field(struct anv_push_constants, cs.base_work_group_id));
anv_load_driver_uniform(b, 3, cs.base_work_group_id[0]);
nir_def_rewrite_uses(&intrin->def, base_workgroup_id);
return true;
@ -1845,10 +1827,7 @@ lower_ray_query_globals(nir_builder *b, nir_intrinsic_instr *intrin,
{
b->cursor = nir_instr_remove(&intrin->instr);
nir_def *rq_globals =
nir_load_push_constant(b, 1, 64, nir_imm_int(b, 0),
.base = offsetof(struct anv_push_constants, ray_query_globals),
.range = sizeof_field(struct anv_push_constants, ray_query_globals));
nir_def *rq_globals = anv_load_driver_uniform(b, 1, ray_query_globals);
nir_def_rewrite_uses(&intrin->def, rq_globals);
return true;

44
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -26,8 +26,6 @@
#include "compiler/brw_nir.h"
#include "util/mesa-sha1.h"
#define sizeof_field(type, field) sizeof(((type *)0)->field)
void
anv_nir_compute_push_layout(nir_shader *nir,
const struct anv_physical_device *pdevice,
@ -73,8 +71,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
desc_surface_offsets);
push_start = MIN2(push_start, base);
push_end = MAX2(push_end, base +
sizeof_field(struct anv_push_constants,
desc_surface_offsets));
anv_drv_const_size(desc_surface_offsets));
if (desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
!pdevice->uses_ex_bso) {
@ -82,8 +79,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
surfaces_base_offset);
push_start = MIN2(push_start, base);
push_end = MAX2(push_end, base +
sizeof_field(struct anv_push_constants,
surfaces_base_offset));
anv_drv_const_size(surfaces_base_offset));
}
break;
}
@ -109,16 +105,18 @@ anv_nir_compute_push_layout(nir_shader *nir,
* the shader.
*/
const uint32_t push_reg_mask_start =
offsetof(struct anv_push_constants, push_reg_mask[nir->info.stage]);
const uint32_t push_reg_mask_end = push_reg_mask_start + sizeof(uint64_t);
anv_drv_const_offset(push_reg_mask[nir->info.stage]);
const uint32_t push_reg_mask_end = push_reg_mask_start +
anv_drv_const_size(push_reg_mask[nir->info.stage]);
push_start = MIN2(push_start, push_reg_mask_start);
push_end = MAX2(push_end, push_reg_mask_end);
}
if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
const uint32_t fs_msaa_flags_start =
offsetof(struct anv_push_constants, gfx.fs_msaa_flags);
const uint32_t fs_msaa_flags_end = fs_msaa_flags_start + sizeof(uint32_t);
anv_drv_const_offset(gfx.fs_msaa_flags);
const uint32_t fs_msaa_flags_end = fs_msaa_flags_start +
anv_drv_const_size(gfx.fs_msaa_flags);
push_start = MIN2(push_start, fs_msaa_flags_start);
push_end = MAX2(push_end, fs_msaa_flags_end);
}
@ -131,8 +129,8 @@ anv_nir_compute_push_layout(nir_shader *nir,
* push constants one dword less than the full amount including
* gl_SubgroupId.
*/
assert(push_end <= offsetof(struct anv_push_constants, cs.subgroup_id));
push_end = offsetof(struct anv_push_constants, cs.subgroup_id);
assert(push_end <= anv_drv_const_offset(cs.subgroup_id));
push_end = anv_drv_const_offset(cs.subgroup_id);
}
/* Align push_start down to a 32B boundary and make it no larger than
@ -186,10 +184,8 @@ anv_nir_compute_push_layout(nir_shader *nir,
b->cursor = nir_before_instr(&intrin->instr);
nir_def *desc_offset = nir_load_uniform(b, 1, 32,
nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
.base = offsetof(struct anv_push_constants,
desc_surface_offsets),
.range = sizeof_field(struct anv_push_constants,
desc_surface_offsets),
.base = anv_drv_const_offset(desc_surface_offsets),
.range = anv_drv_const_size(desc_surface_offsets),
.dest_type = nir_type_uint32);
desc_offset = nir_iand_imm(b, desc_offset, ANV_DESCRIPTOR_SET_OFFSET_MASK);
if (desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
@ -197,10 +193,8 @@ anv_nir_compute_push_layout(nir_shader *nir,
nir_def *bindless_base_offset = nir_load_uniform(
b, 1, 32,
nir_imm_int(b, 0),
.base = offsetof(struct anv_push_constants,
surfaces_base_offset),
.range = sizeof_field(struct anv_push_constants,
surfaces_base_offset),
.base = anv_drv_const_offset(surfaces_base_offset),
.range = anv_drv_const_size(surfaces_base_offset),
.dest_type = nir_type_uint32);
desc_offset = nir_iadd(b, bindless_base_offset, desc_offset);
}
@ -220,10 +214,8 @@ anv_nir_compute_push_layout(nir_shader *nir,
b->cursor = nir_before_instr(&intrin->instr);
nir_def *pc_load = nir_load_uniform(b, 1, 32,
nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
.base = offsetof(struct anv_push_constants,
desc_surface_offsets),
.range = sizeof_field(struct anv_push_constants,
desc_surface_offsets),
.base = anv_drv_const_offset(desc_surface_offsets),
.range = anv_drv_const_size(desc_surface_offsets),
.dest_type = nir_type_uint32);
pc_load = nir_iand_imm(
b, pc_load, ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
@ -259,7 +251,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
if (robust_flags & BRW_ROBUSTNESS_UBO) {
const uint32_t push_reg_mask_offset =
offsetof(struct anv_push_constants, push_reg_mask[nir->info.stage]);
anv_drv_const_offset(push_reg_mask[nir->info.stage]);
assert(push_reg_mask_offset >= push_start);
prog_data->push_reg_mask_param =
(push_reg_mask_offset - push_start) / 4;
@ -315,7 +307,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
container_of(prog_data, struct brw_wm_prog_data, base);
const uint32_t fs_msaa_flags_offset =
offsetof(struct anv_push_constants, gfx.fs_msaa_flags);
anv_drv_const_offset(gfx.fs_msaa_flags);
assert(fs_msaa_flags_offset >= push_start);
wm_prog_data->msaa_flags_param =
(fs_msaa_flags_offset - push_start) / 4;

6
src/intel/vulkan/anv_nir_lower_load_patch_vertices_in.c
View file

@ -46,11 +46,7 @@ lower_patch_vertices_in_instr(nir_builder *b, nir_intrinsic_instr *load,
nir_def_rewrite_uses(
&load->def,
nir_load_push_constant(
b, 1, 32,
nir_imm_int(b, 0),
.base = offsetof(struct anv_push_constants, gfx.tcs_input_vertices),
.range = sizeof_field(struct anv_push_constants, gfx.tcs_input_vertices)));
anv_load_driver_uniform(b, 1, gfx.tcs_input_vertices));
nir_instr_remove(&load->instr);
return true;

2
src/intel/vulkan/anv_pipeline.c
View file

@ -878,7 +878,7 @@ anv_nir_compute_dynamic_push_bits(nir_shader *shader)
continue;
switch (nir_intrinsic_base(intrin)) {
case offsetof(struct anv_push_constants, gfx.tcs_input_vertices):
case anv_drv_const_offset(gfx.tcs_input_vertices):
ret |= ANV_DYNAMIC_PUSH_INPUT_VERTICES;
break;