3 commits

Author	SHA1	Message	Date
Matt Turner	63181df09b	intel/tools: Don't hardcode notification register ... Previously we parsed a src non-terminal but did nothing with it. Since the WAIT instruction is kind of weird, in that you have to give it the same notification subregister for both destination and source, and it always has an exec size of 1, let's parse a destination instead of a source. This way, we can parse a writemask rather than a swizzle in align16 mode, and easily convert the writemask to a swizzle to create the source register. Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>	2020-07-31 12:59:24 -07:00
Matt Turner	1f87106276	intel/tools: Add assembler tests for the cr0 register ... Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>	2020-06-19 02:10:40 +00:00
Sagar Ghuge	4e828bb48a	intel/tools: Add unit tests for assembler ... v1: Pass executable object from meson to test(Dylan Baker) v2: Ignore generated output files from git status(Matt Turner) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>	2019-05-07 14:33:48 -07:00