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intel/tools: Add assembler tests for the cr0 register

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Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5514>
This commit is contained in:
Matt Turner 2020-06-16 17:10:38 -07:00 • committed by Marge Bot
parent e573f21edd
commit 1f87106276
6 changed files with 70 additions and 0 deletions
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7
src/intel/tools/tests/gen11/cr0.asm Normal file
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@ -0,0 +1,7 @@
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };

7
src/intel/tools/tests/gen11/cr0.expected Normal file
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05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff
06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00
06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00

14
src/intel/tools/tests/gen8/cr0.asm Normal file
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and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch };

14
src/intel/tools/tests/gen8/cr0.expected Normal file
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@ -0,0 +1,14 @@
05 80 00 00 00 00 00 30 00 10 00 06 3f fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 3f ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 bf fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 bf ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff
06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00
06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 40 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 40 04 00 00
06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 80 04 00 00

14
src/intel/tools/tests/gen9/cr0.asm Normal file
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@ -0,0 +1,14 @@
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch };
or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch };

14
src/intel/tools/tests/gen9/cr0.expected Normal file
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@ -0,0 +1,14 @@
05 80 00 00 00 00 00 30 00 10 00 06 3f fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 3f ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 bf fb ff ff
05 80 00 00 00 00 00 30 00 10 00 06 bf ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff
05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff
06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00
06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 40 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 40 04 00 00
06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00
06 80 00 00 00 00 00 30 00 10 00 06 80 04 00 00