mesa/src/intel/tools/tests/gen8
Matt Turner 63181df09b intel/tools: Don't hardcode notification register
Previously we parsed a src non-terminal but did nothing with it. Since
the WAIT instruction is kind of weird, in that you have to give it the
same notification subregister for both destination and source, and it
always has an exec size of 1, let's parse a destination instead of a
source. This way, we can parse a writemask rather than a swizzle in
align16 mode, and easily convert the writemask to a swizzle to create
the source register.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>
2020-07-31 12:59:24 -07:00
..
add.asm
add.expected
and.asm
and.expected
asr.asm
asr.expected
bfe.asm
bfe.expected
bfi1.asm
bfi1.expected
bfi2.asm
bfi2.expected
bfrev.asm
bfrev.expected
break.asm
break.expected
cbit.asm
cbit.expected
cmp.asm
cmp.expected
cont.asm
cont.expected
cr0.asm
cr0.expected
csel.asm
csel.expected
else.asm
else.expected
endif.asm
endif.expected
fbh.asm
fbh.expected
fbl.asm
fbl.expected
frc.asm
frc.expected
halt.asm
halt.expected
if.asm
if.expected
lrp.asm
lrp.expected
lzd.asm
lzd.expected
mach.asm
mach.expected
mad.asm
mad.expected
math.asm
math.expected
mov.asm
mov.expected
mul.asm
mul.expected
nop.asm
nop.expected
not.asm
not.expected
or.asm
or.expected
pln.asm
pln.expected
rndd.asm
rndd.expected
rnde.asm
rnde.expected
rndz.asm
rndz.expected
sel.asm
sel.expected
send.asm
send.expected
sendc.asm
sendc.expected
shl.asm
shl.expected
shr.asm
shr.expected
wait.asm intel/tools: Don't hardcode notification register 2020-07-31 12:59:24 -07:00
wait.expected
while.asm
while.expected
xor.asm
xor.expected