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Author SHA1 Message Date
Alyssa Rosenzweig
bc5724faf4 pan/bi: Add bi_print_shader 
Woot! That's the last of it! IR printing is now complete*

*until the IR gets updated when new shiny things are added.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c152d4c835 pan/bi: Add bi_print_block 
Almost there...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c316d1553b pan/bi: Add bi_print_clause 
Again for post-sched purposes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
919cdf15b3 pan/bi: Add bi_print_bundle for printing bi_bundle 
Post-schedule, nops are significnat here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
bde54cb6d3 pan/bi: Add bi_instruction printing 
So we can debug the IR in memory before code emit has happened. We'd
like to have a complete dump of the IR -- neglecting this with Midgard
was one of those mistakes I've regretted so let's get this right for the
first time around.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
aef0f00cbc pan/bi: Move bi_interp_mode_name to bi_print 
Instead of open-coding it in the middle of the disassembler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5d16a8109c pan/bi: Add BIR manipulation routines to bir.c 
New file.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5f7a3ba872 pan/bi: Move some print routines out of the disasm 
These are generally useful for debug of the compiler IR even prior to
code emit; let's share these.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
8ec671801a pan/bi: Add IR iteration macros 
Copypaste from Midgard, for the most part.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
0b26cb194c pan/bi: Add quirks system 
Modeled after the Midgard system. Already we know of two
compiler-visible differences between G52 and G71, so let's keep track so
we can eventually port the compiler to other Bifrost systems.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
07228a6895 pan/bi: Add high-latency property for classes 
This is required to know how to schedule legally, and also influences
some issues relating to RA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
546c301ff6 pan/bi: Add CSEL condition 
Along with src_types, this is enough to represent CSEL.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
47451bb9f1 pan/bi: Add bi_branch data 
For BI_BRANCH, of course. Meshes well with the cfg.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
73c91f14c9 pan/bi: Extract bifrost_branch structure 
It's in the disassembler as bitfields, let's extract to a proper
structure so we can see what's there.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
2afddc4433 pan/bi: Add pred/successors to build CFG 
We'll want this for analysis passes or something, probably.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
d3370bd5a5 pan/bi: Add constants to bi_clause 
Scheduling will have to pay attention to this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
cb3cd8aa56 pan/bi: Add EXTRACT, MAKE_VEC synthetic ops 
These allow translating between the vector I/O and scalar ALUs,
facilitated by an RA dance to ensured contiguous registers are used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
8929fe0c84 pan/bi: Add source type for conversions 
We should now be able to unambiguously represent conversions.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
5896db9578 pan/bi: Add swizzles 
Requires a new field on bifrost_instruction, as well as a new class
property and a new class for the dedicated swizzle ops.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c70a198f24 pan/bi: Clarify special op scheduling 
They're encoded on ADD but eat the full cycle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
fba1d12742 pan/bi: Add clause header fields to bi_clause 
These will be filled out during scheduling (and possibly RA), to be used
when emitting code.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
44ebc275fe pan/bi: Add class-specific ops 
For disambiguating things like min and max within the MINMAX class.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
b5bdd89444 pan/bi: Add constant field to bi_instruction 
Now that we can index it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
a2c1265dd3 pan/bi: Add special indices 
For fixed registers, uniforms, and constants, which bypass the usual SSA
mechanism to map well to the ISA.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
c42002d26f pan/bi: Add dest_type field to bifrost_instruction 
A number of opcodes within a class are disambiguated by type/size, and
whether modifiers make sense or not depends on whether the instruction
acts like a float.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
a35854c5ee pan/bi: Add bi_clause, bi_bundle abstractions 
These will be used during and after scheduling.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
99f3c1f34c pan/bi: Add PAN_SCHED_* flags 
Class (mostly) determines scheduling options.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
9643b9dd5b pan/bi: Add bi_load_vary structure 
For ld_vary in the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
6a7987aba1 pan/bi: Pull out bifrost_load_var 
We're not using this structure yet but we want everything in the ISA
ready for us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
aa2f12de56 pan/bi: Add bi_load structure 
Fills out the class for LD_ATTR, LD_VAR_ADDR

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
b93aec6df1 pan/bi: Add bifrost_minmax_mode field 
We'll open up a union for class specific data, since this is interesting
only to BI_MINMAX. (And even then...)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
d69bf8db62 pan/bi: Add a bifrost_roundmode field 
And a class property signaling it's okay to use.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
bbf41ffb00 pan/bi: Factor out enum bifrost_minmax_mode 
We'll want it from the compiler-side.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
34165c7ec0 pan/bi: Add BI_GENERIC property 
I don't want to have 20 class-specific structures floating around. So
let's derive them all from a common generic ALU type.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
29acd7bd8e pan/bi: Add modifiers to bi_instruction 
Now that we can check if we support them via the class.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
7ac62121e0 pan/bi: Add class properties 
We need to keep track of what specific classes support. For now just
track floating point modifiers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:38 +00:00
Alyssa Rosenzweig
230be61f20 pan/bi: Add src/dest fields to bifrost_instruction 
...along with some helpers to generate indices. The indexing scheme is
mostly a copypaste from Midgard, except we specifically reserve 0 as the
sentinel (midgard uses ~0 for this which has always been a pain point).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
e7dc2a7b9b pan/bi: Add the control flow graph 
We're starting to build up the IR data structures in preparation to get
everything piped through.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
eceaea43e3 pan/bi: Stub out new compiler 
Just enough to pipe in the NIR shader.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
5d3a4e3113 pan/bi: Gut old compiler 
We're making some pretty dramatic design pivots so this early on it'll
be easier to start from scratch, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
eb15525ab7 panfrost: Add note about preloaded varyings 
There's a magic bit in preload_regs which controls this. It doesn't
appear to be supported on G71 but it is on G52. I'd guess G72 supports
it too but I don't have a way to check this.

Needless to say, we'll need a quirks database for this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4061>
 2020-03-05 14:35:37 +00:00
Alyssa Rosenzweig
d0c66869c1 pan/bi: Move some definitions from disasm to bifrost.h 
These are generally useful outside the disassmbler.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
346262ceb6 pan/bi: Structify FMA_FADD 
Just to make it easier to work with.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
4fe5b59a96 pan/bi: Squash LD_ATTR ops together 
*whistles*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
ee957bc0f3 pan/bi: Combine LOAD_VARYING_ADDRESS instructions by type 
It's all a single opcode in fact.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
36fe378f1c pan/bi: Decode ADD_SHIFT properly 
Just like FMA_SHIFT, but with some bits shuffled around.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
8c79c710d4 pan/bi: Identify extended FMA opcodes 
When the top 3 bits of the opcode are 111, it leads to a special
extended opcode mode instead.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
b51468ed9c pan/bi: Add v4i8 mode to FMA_SHIFT 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
2db454bbab pan/bi: Decode FMA_SHIFT properly 
The shift-bitwise ops are fairly configurable, let's decode this the
right way. Choo choo.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00
Alyssa Rosenzweig
67bbaddf7d pan/bi: Move notes on ADD ops to notes file 
Again, we'd like to see just the opcode table more clearly.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>
 2020-03-03 00:03:50 +00:00