Commit graph

163584 commits

Author SHA1 Message Date
Yiwei Zhang
6148ccef63 venus: fix android wsi with global fencing disabled
Fixes: b21e4a7990 ("venus: put android wsi on the sub-optimal path")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>
2022-11-30 01:13:56 +00:00
Sajeesh Sidharthan
8b99e96dc8 radeonsi/vcn: set current pic index correctly
video corruption observed while running decode test for av1
content in chromeos.

solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.

Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>
2022-11-29 23:41:37 +00:00
Karol Herbst
5398dd04bf nir/lower_int64: fix shift lowering
Starting with !19748 lowered 64 bit shifts were showing wrong results for
shifts with insignificant bits set.

nir shifts are defined to only look at the least significant bits. The
lowering has take this into account.

So there are two things going on:
1. the `ieq` and `uge` further down depend on `y` being masked.
2. the calculation of `reverse_count` actually depends on a masked `y` as
   well, due to the `(iabs (iadd y -32))` giving a different result for
   shifts > 31;

Fixes: 41f3e9e5f5 ("nir: Implement lowering of 64-bit shift operations")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19995>
2022-11-29 23:08:53 +00:00
Emma Anholt
83efd336da ci/freedreno: Add another blend_equation_advanced flake.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20066>
2022-11-29 22:42:06 +00:00
Italo Nicola
7dd9bf45b9 panfrost: add GALLIUM_HUD=draw-calls
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20063>
2022-11-29 22:27:07 +00:00
Connor Abbott
0a0a04bdaa tu: Use right enum for compute active_shader_stages
This is VkShaderStageFlags, not VkPipelineStageFlags. Fixes preloading
descriptors for compute dispatches.

Fixes: d862a2ebcb ("turnip: Only emit descriptor loads for active stages in the pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20059>
2022-11-29 22:02:20 +00:00
Emma Anholt
f2414dc2a0 turnip: Drop the cs argument from tu6_emit_cache_flush*().
It's always draw_cs or cs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>
2022-11-29 19:30:25 +00:00
Emma Anholt
939648bbd0 turnip: Clean up a repeated pattern around tu6_emit_flushes().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>
2022-11-29 19:30:25 +00:00
Emma Anholt
43aae91803 turnip: Make tu_emit_cache_flush_ccu manage flush bits like other paths.
Everyone else sets the cache bits directly then calls tu6_emit_flushes on
them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>
2022-11-29 19:30:25 +00:00
Samuel Pitoiset
07dc402a3f radv: inline gfx10_emit_streamout_{begin,end}()
Instead of having 2 different paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19632>
2022-11-29 16:50:13 +00:00
Roman Stratiienko
09ac29cca9 meson: Enable system_has_kms_drm for android
This allows to build libgbm when  system = 'android'  is set in
the cross_file.

Cc: "22.3" "22.2" mesa-stable
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20033>
2022-11-29 15:01:22 +00:00
Rhys Perry
ae521aaa2a radv: compile GS copy shader after geometry shader
This affects the pipeline feedback durations: GS copy shader compilation
is now included in the GS compilation duration.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry
0cb48ec3b7 radv,aco: remove old streamout code
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry
3a96977542 radv,aco: remove old GS copy shader code
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry
17bd2721e6 radv,aco: implement GS copy shaders using NIR
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry
3ab471a87d radv: make radv_use_llvm_for_stage device parameter const
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry
12becb8839 radv: lower streamout in NIR
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Rhys Perry
19d0403594 radv,aco: export legacy vertex outputs in NIR
This new behaviour will let us insert exports in GS copy shader control
flow.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>
2022-11-29 14:28:11 +00:00
Karmjit Mahil
09eb2a4023 pvr: Add missing valgrind includes and fix unused return value.
On including the header the compiler started throwing warnings
about the return value not being used when setting and getting the
vbits.

This commit adds the missing valgrind related headers and fixes the
warnings caused by including them.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20035>
2022-11-29 14:19:41 +00:00
Erik Faye-Lund
8d3475ab8c docs/zink: document missing max-image requirements
This should bring Zink's documentation up to speed with the previous
commit.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund
2658d02516 mesa/main: verify more texture-limits for GL 4.1
OpenGL 4.1 also increased the minimum 3D and cube texture size as
well as the minimum number of texture-array layers. Let's also
verify these to prevent enbaling too recent GL versions on layered
drivers link Zink, VirGL etc.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund
dc770eb9bb zink: check maxImageDimension1D as well as maxImageDimension2D
According to the docs for PIPE_CAP_MAX_TEXTURE_2D_SIZE, it's the limit
both for 2D *and* 1D textures. So let's take the min of the two vulkan
features here instead of assuming they're the same.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund
1b892c5a7d freedreno: fix PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS for a6xx
We're reporting 2048 for VkPhysicalDeviceLimits::maxImageArrayLayers on
Turnip, so we should be able to use 2048 for OpenGL as well. And that's
the minimum required value for OpenGL 4.1 support.

According to http://vulkan.gpuinfo.org/, it seems like values of 2048
should be possible for at least as low as some Adreno 4xx GPUs. But
since we don't support recent GL versions on those, we this won't make a
big difference. So let's leave that up to someone who actually knows
what they're doing!

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund
d15e71ef3c d3d12: fix return-value for PIPE_CAP_MAX_TEXTURE_3D_LEVELS
D3D12_REQ_TEXTURE3D_U_V_OR_W_DIMENSION is 2^11, not 2^10 like the
comment said, and the code assumed. We need to add one to account for
the base-level.

Let's add a static_assert here to prove that this is the right value.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Erik Faye-Lund
acc0039aec d3d12: fix max-array-layers
We used to need this, because we incorrectly multiplied the cube array
sizes by 6. Now that this has been fixed, we can actually support the
OpenGL 4.1 limit for this.

Fixes: 7118b2136e ("d3d12: Don't multiply cube array sizes by 6")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
2022-11-29 13:35:46 +00:00
Samuel Pitoiset
7e287609e3 radv: use HTILE for VRS image only on GFX10.3
Based on registers, GFX11 no longer uses HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>
2022-11-29 12:19:40 +00:00
Samuel Pitoiset
e3d3fb2e69 radv: do not clear VRS_HTILE_ENCODING on GFX11
This field no longer exists.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>
2022-11-29 12:19:40 +00:00
Sarah Walker
2673d0f8b2 pvr: Query kernel for free list max size
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19976>
2022-11-29 10:10:16 +00:00
Connor Abbott
5e5c42ebb5 tu: Fix fault with variable-count inline uniform blocks
This seems to have been triggered by some recent CTS changes which
changed the random number generation. I'm seeing context faults in
dEQP-VK.binding_model.descriptorset_random.sets4.dynindexed.ubolimitlow.sbolimitlow.sampledimghigh.lowimgnotex.iublimitlow.nouab.comp.noia.0
that are fixed by this.

Fixes: 37cde2c634 ("tu: Rewrite inline uniform implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20039>
2022-11-29 09:42:52 +00:00
Aditya Swarup
6080dce4d8 intel/isl: Add MOCS settings for MTL platforms
Add MOCS settings for Xe platforms based on cache settings for L3/L4
and display.

Rework:
 * Jordan: Use intel_device_info_is_mtl()

BSpec: 45101
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20045>
2022-11-29 00:36:41 -08:00
Mauro Rossi
ea10b0fc7a AOSP: Add intel_hasvk vulkan library suffix
Required to correctly install vulkan.intel_hasvk.so module
after commit 50013ca9 ("intel: add a hasvk vulkan driver")

In order to set property ro.hardware.vulkan as 'intel_hasvk' for the correct iGPU parts at init stage,
i915 'graphics version' can only be detected by means of /sys/kernel/debug/dri/0/i915_capabilities
and debugfs needs to be mounted at early-init stage

https://review.lineageos.org/c/LineageOS/android_device_lge_g3-common/+/19875

Cc: "22.3" mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20048>
2022-11-29 09:05:17 +01:00
Qiang Yu
3507cdc59c ac/nir: legacy vs/gs use nir_xfb_info to replace pipe_stream_output_info
pipe_stream_output_info is built from nir_xfb_info, why not just use
nir_xfb_info directly.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20015>
2022-11-29 03:28:42 +00:00
Jianxun Zhang
59b29c5fc4 iris: Use devinfo::has_flat_ccs instead of verx10
The assumption that GFX12.5 devices don't have AUX map is
invalid since MTL's introduction.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>
2022-11-29 02:47:44 +00:00
Jianxun Zhang
93baad8047 intel/dev: Set 'has_flat_ccs' flag for DG2
The code paths of flat ccs should be working on DG2 because
they are routed by other conditions like GFXVer so far. But
using this flag is the intended way, and we need to have
this change prior to updating these conditions with the flag.

Ref: 5262475242 ("intel/dev: Add a has_flat_ccs flag")

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20043>
2022-11-29 02:47:44 +00:00
Jordan Justen
4db33adf9d intel/isl: Disable CCS on MTL
MTL requires some ccs/aux-map changes from Jianxun Zhang, which are
still in progress. So, for now we disable ccs on MTL.

Rework:
 * Drop change in isl_surf_supports_ccs (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20046>
2022-11-28 17:09:52 -08:00
Jordan Justen
cbae305258 anv, iris: Make use of devinfo::has_caching_uapi
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>
2022-11-28 21:54:20 +00:00
Jordan Justen
ed84f163ff intel/dev: Add devinfo::has_caching_uapi (and disable for dg1 and dg2+)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19911>
2022-11-28 21:54:20 +00:00
David Heidelberg
0213750e6d ci/alpine: disable mold on Alpine builds
All the timeouts started close to Mold linking phase, disable it.

See:
 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/32502446
 - https://gitlab.freedesktop.org/mesa/mesa/-/jobs/32465151

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20032>
2022-11-28 20:53:37 +00:00
Thong Thai
afcff6f333 radeonsi/vcn/enc: add encoder statistics support
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19512>
2022-11-28 19:58:41 +00:00
Thong Thai
2d1bd619df frontends/va: add ability for encoder to output statistics
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19512>
2022-11-28 19:58:41 +00:00
Asahi Lina
022d03013a ail: Split off test-miptree.cpp from test-layout.cpp
Keep test-layout.cpp for the simple smoke tests, and move the big pile
of miptree tests to its own file.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
d0532196a2 ail: Add uncompressed twiddled texture sizing tests
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
50ee22f5a5 ail: Rename test-compression.cpp to test-comp-twiddled.cpp
To better align with the analogous test-uncomp-twiddled.cpp

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
c52d4bef2d ail: Add more compression size test cases
Also sort the table in a consistent way, to make it easier to add
tests without creating duplicates in the future.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
c39ca7007f ail: Fix logic for buffer alignment
It turns out that specifically Z/S single-layer textures have the main
miptree padded to the page size, but not others.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
ecdcb3e1aa ail: Fix compression metadata buffer sizing corner cases
Although the metadata is possibly one byte per 8x4 block, the
logical block size for compression/allocation is a 16x16 block,
so align to that. Also align the initial dimensions to that size,
and change the minification to a simple DIV_ROUND_UP.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
112830f1a0 asahi: Pass through layer alignment flag to the hardware
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Asahi Lina
d88b546e65 ail: Introduce layer_alignment flag
The hardware uses this flag to determine whether layer strides are
implicitly aligned to the page size or not.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 19:50:18 +00:00
Rhys Perry
974358a8c1 radv/llvm: add clip distance outputs manually if they're missing
It's possible that undef is written to clip/cull distance outputs and
they're eliminated, and we never set any position export to done=1 because
outinfo->pos_exports was calculated with the expectation that clip/cull is
exported.

Eliminating the export and fixing the done=1 bit hangs because the
hardware is still expecting clip/cull distances.

Fixes dEQP-VK.rasterization.provoking_vertex.transform_feedback.first.line_list
hang with LLVM.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19200>
2022-11-28 19:18:50 +00:00
Georg Lehmann
7aa94efe82 aco: Combine constant bit test to s_bitcmp.
Foz-DB Navi21:
Totals from 73988 (54.84% of 134913) affected shaders:
VGPRs: 2959768 -> 2959752 (-0.00%)
SpillSGPRs: 10250 -> 10697 (+4.36%); split: -0.64%, +5.00%
SpillVGPRs: 2326 -> 2291 (-1.50%); split: -2.24%, +0.73%
CodeSize: 261339476 -> 261045912 (-0.11%); split: -0.12%, +0.00%
Scratch: 239616 -> 238592 (-0.43%)
Instrs: 49214044 -> 49188242 (-0.05%); split: -0.06%, +0.00%
Latency: 413214139 -> 413296229 (+0.02%); split: -0.03%, +0.05%
InvThroughput: 71741622 -> 71786300 (+0.06%); split: -0.07%, +0.13%
VClause: 856838 -> 856973 (+0.02%); split: -0.01%, +0.02%
SClause: 1504502 -> 1504567 (+0.00%); split: -0.01%, +0.02%
Copies: 4058433 -> 4060424 (+0.05%); split: -0.03%, +0.08%
Branches: 1502953 -> 1502945 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 3081927 -> 3081531 (-0.01%); split: -0.02%, +0.01%
PreVGPRs: 2513990 -> 2513992 (+0.00%)

The vast majority of instruction count regressions are caused by parallel-rdp.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18870>
2022-11-28 18:43:53 +00:00