Commit graph

217560 commits

Author SHA1 Message Date
Mike Blumenkrantz
5ca94eabec ntv: stop explicitly tracking variables for samplers/images
it's technically legal for duplicates to exist so long as they are never
accessed, so this was always wrong

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39488>
2026-01-23 18:44:07 +00:00
Mike Blumenkrantz
ec39a48901 ntv: emit extra decorations for matrix members of structs
this is awful.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39488>
2026-01-23 18:44:06 +00:00
Mike Blumenkrantz
e61444e33f zink: break out ntv into separate meson dep
no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39488>
2026-01-23 18:44:06 +00:00
Gurchetan Singh
9c511a1fa5 gfxstream: fixes related to -Wmissing-prototypes
- the vkSetDebugMetadataAsyncGOOGLE command should
  not have an entry in the function table: it
  leads to missing prototype errors

- Make gfxstream respect cpp_msvc_compat_args, since
  it is a C++ project.  -Wmissing-prototypes will be
  made a cpp error *eventually*.

Reviewed-by: Aaron Ruby <aruby@qnx.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39418>
2026-01-23 18:06:01 +00:00
Gurchetan Singh
0f582b0268 gallium: fix sometimes-uninitialized warning
Otherwise:

gallium/auxiliary/gallivm/lp_bld_nir_soa.c:2394:7:
 error: variable 'opname' is used uninitialized whenever switch default is taken

is observed.

Reviewed-by: @LingMan
Fixes: 12bceb228a ("gallivm: let reduce ops use llvm intrinsics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39418>
2026-01-23 18:06:01 +00:00
Connor Abbott
09b9205117 tu: Fix FDM texel size calculation
Some checks are pending
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It turns out that it was intended to round down when dividing the
framebuffer size by FDM size and all other implementations of
VK_EXT_fragment_density_map did that. We followed the spec, which
doesn't say to round (which is equivalent to rounding up), but the spec
will be updated to reflect the intended behavior.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39434>
2026-01-23 17:19:04 +00:00
Connor Abbott
fbc97b24d1 ir3: Fix branchstack max_waves calculation
There were a few missing things here:

- The max_waves can be odd even when wavesize_granularity = 2, unlike
  with registers, so we should not multiply by wavesize_granularity.
  This means we have to double branchstack_size to compensate.
- The actual limit was half what it should be on a6xx-a7xx, because when
  I originally calculated this computerator was using the wrong
  branchstack units. We need to double branchstack_size again.
- We should limit the branchstack based on max_branchstack and align it
  to 2 on a5xx+, as we do when programming the HW.
- On a8xx the limit is doubled compared to a7xx to compensate for losing
  wave128.

Fix all of these.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39468>
2026-01-23 16:54:32 +00:00
Connor Abbott
f5ea8b9a0b ir3: Split out max_branchstack and branchstack_size
One is the maximum size per wave and the other is the size per uSP (i.e.
"core"). They happened to be the same before, but actually they are
different limits in the HW.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39468>
2026-01-23 16:54:32 +00:00
Connor Abbott
c569fb5669 freedreno, ir3: Fix branchstack register definitions on a5xx+
The branchstack starts one bit lower, and we have to round to the next
even value instead of dividing by 2. This matches the actual HW
definition and will make the next commits simpler.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39468>
2026-01-23 16:54:31 +00:00
Samuel Pitoiset
b30f780c4f vulkan: update spec to 1.4.340
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39476>
2026-01-23 16:07:30 +00:00
Samuel Pitoiset
bb4157ad31 spirv: Update the JSON and headers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39476>
2026-01-23 16:07:30 +00:00
Erik Faye-Lund
2c7dbf6477 pvr: prepare pvr_winsys_compute_ctx_create_info for multi-arch
Some checks are pending
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Reviewed-by: Ashish Chauhan <ashish.chauhan@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39348>
2026-01-23 12:40:22 +00:00
Erik Faye-Lund
a98e22d0f7 pvr: prepare pvr_winsys_render_ctx_create_info for multi-arch
Reviewed-by: Ashish Chauhan <ashish.chauhan@imgtec.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39348>
2026-01-23 12:40:22 +00:00
Erik Faye-Lund
2736dd1220 pvr/srv: define per-arch winsys-ops
This moves the dispatching for each winsys function out to arch-specific
variants of the pvr_winsys_ops structure instead. This gets rid of some
needless complexity, and should make the code easier to maintain in the
long run.

Reviewed-by: Ashish Chauhan <ashish.chauhan@imgtec.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39348>
2026-01-23 12:40:21 +00:00
Erik Faye-Lund
65f06dd25b pvr/srv: query full pvr_device_info on winsys init
This will be helpful in the next commit.

Reviewed-by: Ashish Chauhan <ashish.chauhan@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39348>
2026-01-23 12:40:20 +00:00
Erik Faye-Lund
67950d9021 pvr: avoid needless dispatches in powervr winsys
All uses of PVR_ARCH_DISPATCH in the powervr winsys were due to needing
to reach the kmd_stream.xml definitions. However, this isn't quite
enough to do this multi-arch; we also need to widen the interface to
pass extra context-switching information for future GPUs.

But, doing this with the per-arch infrastructure isn't a huge gain,
because all of this code runs during context-init. So let's walk things
a bit, and drop the dispatching here.

This does mean we need to stop using kmd_stream.xml definitions; I don't
think this is a huge loss; we're mostly open-coding the firmware
interface here anyway.

Unfortunately, the same is not the case in the pvrsrvkm winsys, because
the kernel driver used there doesn't abstract away the same HW details,
so we'll need to set up a bunch of things based on HW definitions. So
let's take a different approach there.

Reviewed-by: Ashish Chauhan <ashish.chauhan@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39348>
2026-01-23 12:40:20 +00:00
Erik Faye-Lund
2ebf1dcdc1 pvr: drop needless include
This isn't in use; let's drop it.

Reviewed-by: Ashish Chauhan <ashish.chauhan@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39348>
2026-01-23 12:40:19 +00:00
Danylo Piliaiev
1d6fe66989 tu: Fix typo in min bounds calculation of FDM scissors
Fixes: fec372dfa5 ("tu: Implement FDM viewport patching")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39461>
2026-01-23 11:44:43 +00:00
Tapani Pälli
6f020a4048 iris: implement steps to disable RHWO for Wa_14024015672
Disable RHWO by default for singlesample draws and for MSAA
draws if a drirc key is set (avoid perf hit if not needed).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39404>
2026-01-23 11:10:07 +00:00
Tapani Pälli
f66ff97d58 drirc/anv: implement steps to disable RHWO for Wa_14024015672
Disable RHWO by default for singlesample draws and for MSAA
draws if a drirc key is set (avoid perf hit if not needed).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39404>
2026-01-23 11:10:07 +00:00
Tapani Pälli
055a89cffb intel/genxml: bring some missing fields to gen125.xml
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39404>
2026-01-23 11:10:07 +00:00
Tapani Pälli
840e6e855b anv: add handling for Wa_14026600921
This is the Xe3 version of the earlier workaround.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39404>
2026-01-23 11:10:07 +00:00
Tapani Pälli
c75309c8f1 intel/dev: update mesa_defs.json from workaround database
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39404>
2026-01-23 11:10:07 +00:00
Juan A. Suarez Romero
d7ed5ba0e7 broadcom/ci: remove duplicate entries
Some checks are pending
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Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39458>
2026-01-23 10:44:30 +00:00
Juan A. Suarez Romero
d18aa3eee4 broadcom/ci: re-evaluate all the flakes
Review all the flakes and remove those that weren't seen for a long
time, and add also new ones.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39458>
2026-01-23 10:44:30 +00:00
Juan A. Suarez Romero
7c26cbabd2 broadcom/ci: rename rusticl job
Highlight this job will run the full list of piglit OpenCL tests.

It also increases the timeout for rpi4 GPU.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39458>
2026-01-23 10:44:29 +00:00
Juan A. Suarez Romero
b1aa16df81 broadcom/ci: re-adjust fractions
So the non-full jobs are executed under 15 minutes budget.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39458>
2026-01-23 10:44:29 +00:00
Juan A. Suarez Romero
8f5d6d2575 broadcom/ci: re-evaluate timeout tests
Check the tests marked as timeout to see if they aren't timeout anymore,
and add new ones if required.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39458>
2026-01-23 10:44:29 +00:00
Juan A. Suarez Romero
05d444bffc broadcom/ci: remove asan failures from rpi3 and rpi4
ASAN jobs are not executed anymore on these GPUs.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39458>
2026-01-23 10:44:29 +00:00
Georg Lehmann
5827de9cd6 aco/gfx12: use 64bit add/sub to swap sgprs
Not writing SCC requires less instructions and gives the scheduler more
freedom.

Foz-DB GFX1201:
Totals from 114 (0.14% of 82179) affected shaders:
Instrs: 276265 -> 275791 (-0.17%)
CodeSize: 1460504 -> 1458504 (-0.14%)
Latency: 902933 -> 902548 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 166517 -> 166512 (-0.00%)
SClause: 6703 -> 6698 (-0.07%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39329>
2026-01-23 10:13:19 +00:00
Georg Lehmann
763b4f1f0a radv/gfx11: add a RADV_PERFTEST flag to expose bfloat16 cmat
This doesn't pass CTS because of precision issues, but might still be useful.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14699
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39456>
2026-01-23 09:41:20 +00:00
Rob Clark
455b692e4f freedreno: Force single wavesize if double threadsize is unsupported
Some checks are pending
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Turns out ir3 isn't enforcing this itself.

Fixes: c323848b0b ("ir3, tu: Plumb through support for per-shader robustness")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39470>
2026-01-23 00:38:10 +00:00
Rob Clark
53b879ac58 freedreno/common: Fix gen8 EFU float control
Some checks are pending
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This reg should be programmed to zero like previous gens.

Fixes: 6e3598177b ("freedreno/common: Add A840 and X2-85")
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39467>
2026-01-22 23:49:41 +00:00
Sagar Ghuge
6aa3b70382 anv: Mark RootNodeOffset at 256B always
This commit change the BVH layout a little so that we can load the BVH
offset as constant rather than reading from memory.

We have to force the instance leaves pointer at the end which gets used
in copy.comp shader.

Totals:
Instrs: 54798 -> 54728 (-0.13%)
Send messages: 3854 -> 3847 (-0.18%)
Cycle count: 1915106 -> 1913954 (-0.06%); split: -0.07%, +0.01%
Non SSA regs after NIR: 18594 -> 18575 (-0.10%)

Totals from 7 (7.37% of 95) affected shaders:
Instrs: 5532 -> 5462 (-1.27%)
Send messages: 367 -> 360 (-1.91%)
Cycle count: 132592 -> 131440 (-0.87%); split: -1.01%, +0.14%
Non SSA regs after NIR: 1989 -> 1970 (-0.96%)

PERCENTAGE DELTAS Shaders   Instrs  Send messages Cycle count Non SSA regs after NIR
q2rtx-rt-pipeline 95        -0.13%      -0.18%       -0.06%           -0.10%
--------------------------------------------------------------------------------------
All affected      7         -1.27%      -1.91%       -0.87%           -0.96%
--------------------------------------------------------------------------------------
Total             95        -0.13%      -0.18%       -0.06%           -0.10%

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39106>
2026-01-22 23:20:04 +00:00
Marek Olšák
0fc48ddfc6 radeonsi: disable 2D compute dispatch SE interleaving
It makes several cases of image blits slower, but it doesn't make
any of them faster.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:41 +00:00
Marek Olšák
fbcc8cae81 radeonsi: test bigger sizes for AMD_TEST=dmaperf
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:41 +00:00
Marek Olšák
5ce74df3f3 radeonsi: add faster color clear for gfx12
Compute shader image clears are pretty good on gfx12.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:41 +00:00
Marek Olšák
0af1392d29 radeonsi: don't use pipe_surface_size in clears
pipe_surface_size is only special for compressed textures, which can't
occur here.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:41 +00:00
Marek Olšák
ebeb904c95 ac,radeonsi: set optimal COMPUTE_DISPATCH_INTERLEAVE for buffer clears/copies
Small buffer clears are a bit faster now.

The numbers were tuned specifically for this compute shader.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:39 +00:00
Marek Olšák
a5e1d31dad ac/nir/meta: tune 12B clear buffer performance for gfx12
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:39 +00:00
Marek Olšák
9257cf04a1 ac/nir/meta: tune image clear & copy performance for gfx12
Compute shaders are the fastest for all copies and some clears.
Note that this is a very different compute shader than the one in RADV.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39290>
2026-01-22 22:28:38 +00:00
Natalie Vock
15328a5ef3 aco: Fix parameter stack size calculation
Some checks are pending
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This only accounted for 1/32 (or 1/64) of the actual parameter size. In
some cases this meant that some threads were smashing other threads'
stacks.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39455>
2026-01-22 22:02:31 +00:00
Mike Blumenkrantz
6474af3b42 zink: re-allow transient images during blitting
now that transient images are a more complete mechanism, this should
in theory be okay and also accounts for the case where
a framebuffer contains mixed msrtt textures and plain multisampled textures

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39464>
2026-01-22 20:51:53 +00:00
Mary Guillemard
457149a48e nvk/nvkmd: Do not limit exec_push count in nvkmd_nouveau_exec_ctx
Previously, we were allowing up to 1024 entries to be accumulated and
pushed. Nouveau kernel side always report 510 entries but we are going
to increase this at some point.

This makes it so that we now dynamically allocate
nvkmd_nouveau_exec_ctx::req_push.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39239>
2026-01-22 20:35:03 +00:00
Valentine Burley
6d69d7e6bf tu: Implement VK_EXT_device_memory_report
This is a minimal implementation reporting only device memory allocations
and frees.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14687
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39406>
2026-01-22 20:11:24 +00:00
Valentine Burley
8e078fad2a tu: Assign stable unique_id to buffer objects
Add a unique_id field to struct tu_bo, to ensure that every bo has a
unique identifier.

On KGSL, importing the same dma-buf multiple times produces distinct GEM
handles, which violates the VK_EXT_device_memory_report requirement that
the object ID uniquely identifies the underlying memory.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39406>
2026-01-22 20:11:23 +00:00
Silvio Vilerino
4b366f8824 d3d12: Add HAVE_GALLIUM_D3D12_VIDEO guards for d3d12_video_encoder_set_max_async_queue_depth/d3d12_video_encoder_get_last_slice_completion_fence
Some checks are pending
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Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14709
Fixes: e55b2b5064 ("d3d12: Add get_video_enc_last_slice_completion_fence interop")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39457>
2026-01-22 19:16:53 +00:00
Silvio Vilerino
237313a243 d3d12: Add missing using Microsoft::WRL:ComPtr in d3d12_context_common
Fixes: b06b2fbaba ("d3d12: Remove Agility v717 guards for features now available in v618")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39457>
2026-01-22 19:16:52 +00:00
Dylan Baker
0380c1228e bin/pick: When the main widget is replaced, trigger a redraw
The docs clearly say this, and though it used to just work that seems to
have been a coincidence rather than being correct.

CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39459>
2026-01-22 19:11:21 +00:00
Eric Engestrom
21829c9f7e pick-ui: update for python 3.14 support
```
Traceback (most recent call last):
  File "bin/pick-ui.py", line 31, in <module>
    loop = urwid.MainLoop(u.render(), PALETTE, event_loop=evl, handle_mouse=False)
                          ~~~~~~~~^^
  File "bin/pick/ui.py", line 196, in render
    asyncio.ensure_future(self.update())
    ~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^
  File "/usr/lib64/python3.14/asyncio/tasks.py", line 730, in ensure_future
    loop = events.get_event_loop()
  File "/usr/lib64/python3.14/asyncio/events.py", line 715, in get_event_loop
    raise RuntimeError('There is no current event loop in thread %r.'
                       % threading.current_thread().name)
RuntimeError: There is no current event loop in thread 'MainThread'.
```

Of the 3 dependencies, only urwid actually needs to be updated, but
while at it let's pick the latest of each.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39452>
2026-01-22 19:04:02 +00:00