When new context was created, shared_mem_size was getting overwritten.
This fixes glretrace failure seen with manhattan, aztec and BASS2_intro
apitraces
Fixes: 247c61f2d0 ('svga: Add support for compute shader, shader buffers and image views')
Tested with glretrace, piglit
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit dd6793ec9218782b1b716a87582d7219bae4e75f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14870>
(cherry picked from commit 9230b28533)
We didn't remove desc set from the pool's list if pool was
host_memory_base. On the other hand in there is no point in removing
desc set from the list in DestroyDescriptorPool/ResetDescriptorPool.
Fixes: da7a4751
("turnip: Drop references to layout of all sets on pool reset/destruction")
Fixes cts tests:
dEQP-VK.api.buffer_marker.graphics.default_mem.bottom_of_pipe.memory_dep.draw
dEQP-VK.api.buffer_marker.graphics.default_mem.bottom_of_pipe.memory_dep.dispatch
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14855>
(cherry picked from commit 183bc15bdb)
IRIS_BATCH_BLITTER isn't supported prior to Tigerlake; in general,
batches may not be supported on all hardware. In most cases, querying
them is harmless (if useless): they reference nothing, have no commands
to flush, and so on. However, the fence code does need to know that
certain batches don't exist, so it can avoid adding inter-batch fences
involving them.
This patch introduces a new iris_foreach_batch() iterator macro that
walks over all batches that are actually supported on the platform,
while skipping the others. It provides a central place to update should
we add or reorder more batches in the future.
Fixes various tests in the piglit.spec.ext_external_objects.* category.
Thanks to Tapani Pälli for catching this.
Fixes: a90a1f15 ("iris: Create an IRIS_BATCH_BLITTER for using the BLT command streamer")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14834>
(cherry picked from commit fd0e4aedeb)
Without this change LLVM 12 hits this error:
"""
LLVM ERROR: Error while trying to spill SGPR0_SGPR1 from class SReg_64:
Cannot scavenge register without an emergency spill slot!
"""
when running glcts KHR-GL46.arrays_of_arrays_gl.AtomicUsage test.
Fixes: 9ff086052a ("radeonsi: unroll loops of up to 128 iterations")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14848>
(cherry picked from commit eaa87b1a46)
The Mesh pipeline is implemented as a variant of the
regular (primitive) Graphics Pipeline.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
This is a nontrivial chunk of code that makes for a nice dis/assembler test
case (and caught a bug already...). Add it to the observatory.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
The swizzle handling in ISA.xml was broken in a bunch of place. Now that
we've fixed these issues, let's add tons of tests to validate.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two
bytes. The definition is the same as Bifrost. Let's call this a half-swizzle
since we need a name, and it is indeed half a swizzle...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
The lane select is in bit 28, this is covered by the "16-bit swizzle" mode.
However, the source type isn't inferred from the name in valhall.py, so
explicitly annotate the source as 16-bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
Per primitive & attachment shading rate support added.
v2: Rebase on KHR_dynamic_rendering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
For instance, the current code in genX_cmd_buffer.c assumes that the
depth/stencil attachments & resolves will be at the end of all
attachments, but that won't be the case anymore with fragment rate
shading.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.
v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)
v3: Drop unused macro (Nanley)
s/isl_to_gen/isl_encode/ (Nanley)
Remove pitch alignment 128B constraint already covered by tiling (Nanley)
Move some asserts together (Nanley)
v4: Disable miptail for now (Nanley)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
