Rename it to set_src_i20 and fix the assert to allow negative signed
values. Also, add a new set_src_f20 helper with the correct semantics
for float immediates. Finally, get rid of some bogus shifting in the
ALU code.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
Only encode some instructions.
some TODO:
- SM50 specific legalizer
- Cleaner ALU encoding (there is multiple form of encoding depending of
the instruction)
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
In some cases we are using an initramfs image that pre-mounts some of
the directories, so let's skip them in the next stage.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26552>
In some cases we can have the config.txt boot file already available in
the tftp folder.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26552>
Bindings are not necessarily globally unique, and even the location
where we were trying to read the binding value out of is a union, so
we could be trying to compare binding values against data for other
arg types.
Instead, use the arg metadata offset, which is globally unique and
outside of the union.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26555>
Since nir_opt_algebraic runs on its own results, if the driver doesn't
have [su]dot_4x8_[ui]add then the [su]dot_4x8_[ui]add lowering rules
will kick in and lower that to what we had originally.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
With this commit, NAK now takes on a more Cargo-like structure with
things split better into crates:
- bitview/
- lib.rs // Formerly bitview.rs
- nak/
- lib.rs // Only pulls stuff into the module
- api.rs // Formerly nak.rs
- ...
- nvfuzz/
- main.rs // Formerly nvfuzz.rs
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26546>
Batch bos are always allocated with ANV_BO_ALLOC_HOST_CACHED_COHERENT
so there is no need to do cflush calls.
But if we ever decide to change that anv_bo_needs_host_cache_flush()
will make sure cflush is called.
Outside of batch bos, this patch is also removing the
intel_flush_range() call from anv_QueuePresentKHR because
device->debug_frame_desc is offset of workaround_bo that is also
allocated as ANV_BO_ALLOC_HOST_COHERENT.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
In platforms with LLC we can promote all bos to cached+coherent
without any performance penality.
On the up side CPU reads can hit cache this way.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
As suggested by Lionel, here adding ANV_BO_ALLOC_HOST_COHERENT
and with that ANV_BO_ALLOC_HOST_CACHED_COHERENT is now defined by
(ANV_BO_ALLOC_HOST_COHERENT | ANV_BO_ALLOC_HOST_CACHED).
In some callers of anv_device_alloc_bo() was necessary to add
ANV_BO_ALLOC_HOST_COHERENT as no other flag was set and that
was the default behavior up to now.
A change that could look not related is the removal of the
intel_flush_range() in anv_device_init_trivial_batch(), that was done
because trivial_batch_bo is HOST_COHERENT so no flush is necessary.
And it did not made sense to make it ANV_BO_ALLOC_HOST_CACHED_COHERENT
as it was never read in CPU.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
Kernel versions without DRM_I915_QUERY_MEMORY_REGIONS support will
take a different code path in i915_gem_create() that lacks the
i915_gem_set_caching() call to make cached bos in gen9 lp 1 way
coherent.
Fixes: fc0acf6d90 ("anv: Move i915 specific gem_set_caching to backend")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26457>
- Adds new 'all' value to the video-codecs option
- Adds 'all_free' value to video-codecs and sets
it as default value for non patent-encumbered
codecs, restoring the behavior for these codecs
before existing as options in commit 7b22dd8bfd
Fixes: 7b22dd8bfd ("meson: add vp9 and av1 codec support options")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26320>
This fields are required to be set because those are used by
XY_FAST_COLOR_BLT instruction.
Right now it is not set causing applications to abort because
DestinationMOCS is required to be non-zero.
This fixes at least piglit@ext_external_objects-vk-image-display on MTL.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26502>
On newer platforms (Arrowlake and above) we can issue a
EXECUTE_INDIRECT_DRAW that allows us to:
* Skip issuing mi load/store instructions for indirect parameters
* Skip doing the indirect draw unroll on the CPU side when the
appropriate stride is passed
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26178>
This is now supported and this allows Zink to enable full ds3 mode for
even less stuttering. DXVK also uses dynamic alpha to coverage
sometimes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
Replacement in try_eval_const_alu() doesn't work because the replacements
are always scalar. The callers also always give a scalar dest.
This is encountered when compiling a Redout shader under ASan.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Fixes: bc170e895f ("nir/loop_analyze: Use try_eval_const_alu and induction variable basis info")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26225>
It has been in a rough few days for that farm and it doesn't seem to be
able to handle the load.
Unfortunately we need to consider it down so that it stops blocking
merges.
