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nak: Use OpLop2 and OpPSetP pre-SM70
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26114>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
36e80caac9
commit
e404877a02
5 changed files with 220 additions and 60 deletions
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@ -24,10 +24,7 @@ pub trait Builder {
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}
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}
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fn lop2_to(&mut self, dst: Dst, op: LogicOp3, x: Src, y: Src) {
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/* Only uses x and y */
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assert!(!op.src_used(2));
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fn lop2_to(&mut self, dst: Dst, op: LogicOp2, mut x: Src, mut y: Src) {
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let is_predicate = match dst {
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Dst::None => panic!("No LOP destination"),
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Dst::SSA(ssa) => ssa.is_predicate(),
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@ -36,18 +33,54 @@ pub trait Builder {
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assert!(x.is_predicate() == is_predicate);
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assert!(y.is_predicate() == is_predicate);
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if is_predicate {
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self.push_op(OpPLop3 {
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dsts: [dst.into(), Dst::None],
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srcs: [x, y, Src::new_imm_bool(true)],
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ops: [op, LogicOp3::new_const(false)],
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});
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if self.sm() >= 70 {
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let mut op = op.to_lut();
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if x.src_mod.is_bnot() {
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op = LogicOp3::new_lut(&|x, y, _| op.eval(!x, y, 0));
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x.src_mod = SrcMod::None;
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}
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if y.src_mod.is_bnot() {
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op = LogicOp3::new_lut(&|x, y, _| op.eval(x, !y, 0));
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y.src_mod = SrcMod::None;
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}
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if is_predicate {
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self.push_op(OpPLop3 {
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dsts: [dst.into(), Dst::None],
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srcs: [x, y, true.into()],
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ops: [op, LogicOp3::new_const(false)],
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});
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} else {
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self.push_op(OpLop3 {
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dst: dst.into(),
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srcs: [x, y, 0.into()],
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op: op,
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});
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}
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} else {
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self.push_op(OpLop3 {
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dst: dst.into(),
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srcs: [x, y, Src::new_zero()],
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op: op,
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});
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if is_predicate {
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let mut x = x;
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let cmp_op = match op {
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LogicOp2::And => PredSetOp::And,
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LogicOp2::Or => PredSetOp::Or,
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LogicOp2::Xor => PredSetOp::Xor,
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LogicOp2::PassB => {
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// Pass through B by AND with PT
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x = true.into();
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PredSetOp::And
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}
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};
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self.push_op(OpPSetP {
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dsts: [dst.into(), Dst::None],
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ops: [cmp_op, PredSetOp::And],
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srcs: [x, y, true.into()],
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});
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} else {
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self.push_op(OpLop2 {
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dst: dst.into(),
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srcs: [x, y],
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op: op,
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});
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}
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}
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}
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@ -259,7 +292,7 @@ pub trait SSABuilder: Builder {
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dst
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}
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fn lop2(&mut self, op: LogicOp3, x: Src, y: Src) -> SSARef {
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fn lop2(&mut self, op: LogicOp2, x: Src, y: Src) -> SSARef {
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let dst = if x.is_predicate() {
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self.alloc_ssa(RegFile::Pred, 1)
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} else {
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@ -315,15 +315,19 @@ impl SM50Instr {
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self.set_field(range, reg.base_idx());
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}
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fn set_reg_src(&mut self, range: Range<usize>, src: Src) {
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assert!(src.src_mod.is_none());
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match src.src_ref {
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fn set_reg_src_ref(&mut self, range: Range<usize>, src_ref: SrcRef) {
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match src_ref {
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SrcRef::Zero => self.set_reg(range, RegRef::zero(RegFile::GPR, 1)),
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SrcRef::Reg(reg) => self.set_reg(range, reg),
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_ => panic!("Not a register"),
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}
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}
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fn set_reg_src(&mut self, range: Range<usize>, src: Src) {
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assert!(src.src_mod.is_none());
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self.set_reg_src_ref(range, src.src_ref);
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}
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fn set_pred_dst(&mut self, range: Range<usize>, dst: Dst) {
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match dst {
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Dst::None => {
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@ -631,6 +635,20 @@ impl SM50Instr {
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self.set_pred_src(39..42, 42, op.cond);
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}
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fn encode_psetp(&mut self, op: &OpPSetP) {
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self.set_opcode(0x5090);
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self.set_pred_dst(3..6, op.dsts[0]);
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self.set_pred_dst(0..3, op.dsts[1]); /* dst1 */
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self.set_pred_src(12..15, 15, op.srcs[0]);
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self.set_pred_src(29..32, 32, op.srcs[1]);
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self.set_pred_src(39..42, 42, op.srcs[2]);
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self.set_pred_set_op(24..26, op.ops[0]);
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self.set_pred_set_op(45..47, op.ops[1]);
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}
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fn set_mem_type(&mut self, range: Range<usize>, mem_type: MemType) {
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assert!(range.len() == 3);
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self.set_field(
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@ -717,6 +735,63 @@ impl SM50Instr {
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}
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}
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fn encode_lop2(&mut self, op: &OpLop2) {
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if let Some(imm32) = op.srcs[1].as_imm_not_i20() {
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self.set_opcode(0x0400);
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self.set_dst(op.dst);
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self.set_reg_src_ref(8..16, op.srcs[0].src_ref);
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self.set_bit(55, op.srcs[0].src_mod.is_bnot());
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self.set_src_imm32(20..52, imm32);
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self.set_field(
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53..55,
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match op.op {
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LogicOp2::And => 0_u8,
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LogicOp2::Or => 1_u8,
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LogicOp2::Xor => 2_u8,
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LogicOp2::PassB => {
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panic!("PASS_B is not supported for LOP32I");
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}
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},
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);
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} else {
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match &op.srcs[1].src_ref {
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SrcRef::Zero | SrcRef::Reg(_) => {
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self.set_opcode(0x5c40);
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self.set_reg_src_ref(20..28, op.srcs[1].src_ref);
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}
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SrcRef::Imm32(i) => {
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self.set_opcode(0x3840);
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self.set_src_imm_i20(20..39, 56, *i);
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}
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SrcRef::CBuf(cb) => {
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self.set_opcode(0x4c40);
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self.set_src_cb(20..39, cb);
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}
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src1 => panic!("unsupported src1 type for IMUL: {src1}"),
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}
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self.set_dst(op.dst);
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self.set_reg_src_ref(8..16, op.srcs[0].src_ref);
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self.set_bit(39, op.srcs[0].src_mod.is_bnot());
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self.set_bit(40, op.srcs[1].src_mod.is_bnot());
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self.set_field(
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41..43,
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match op.op {
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LogicOp2::And => 0_u8,
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LogicOp2::Or => 1_u8,
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LogicOp2::Xor => 2_u8,
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LogicOp2::PassB => 3_u8,
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},
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);
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self.set_pred_dst(48..51, Dst::None);
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}
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}
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fn encode_shf(&mut self, op: &OpShf) {
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/* TODO: This should happen as part of a legalization pass */
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assert!(op.shift.is_reg_or_zero());
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@ -1645,12 +1720,14 @@ impl SM50Instr {
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Op::IAdd3(op) => si.encode_iadd3(&op),
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Op::Mov(op) => si.encode_mov(&op),
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Op::Sel(op) => si.encode_sel(&op),
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Op::PSetP(op) => si.encode_psetp(&op),
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Op::SuSt(op) => si.encode_sust(&op),
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Op::S2R(op) => si.encode_s2r(&op),
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Op::PopC(op) => si.encode_popc(&op),
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Op::Brev(op) => si.encode_brev(&op),
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Op::Prmt(op) => si.encode_prmt(&op),
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Op::Ld(op) => si.encode_ld(&op),
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Op::Lop2(op) => si.encode_lop2(&op),
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Op::Shf(op) => si.encode_shf(&op),
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Op::F2F(op) => si.encode_f2f(&op),
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Op::F2I(op) => si.encode_f2i(&op),
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@ -774,13 +774,10 @@ impl<'a> ShaderFromNir<'a> {
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b.iadd(srcs[0], srcs[1])
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}
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}
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nir_op_iand => {
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b.lop2(LogicOp3::new_lut(&|x, y, _| x & y), srcs[0], srcs[1])
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}
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nir_op_iand => b.lop2(LogicOp2::And, srcs[0], srcs[1]),
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nir_op_ieq => {
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if alu.get_src(0).bit_size() == 1 {
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let lop = LogicOp3::new_lut(&|x, y, _| !(x ^ y));
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b.lop2(lop, srcs[0], srcs[1])
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b.lop2(LogicOp2::Xor, srcs[0], srcs[1].bnot())
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} else if alu.get_src(0).bit_size() == 64 {
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b.isetp64(IntCmpType::I32, IntCmpOp::Eq, srcs[0], srcs[1])
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} else {
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@ -850,8 +847,7 @@ impl<'a> ShaderFromNir<'a> {
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}
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nir_op_ine => {
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if alu.get_src(0).bit_size() == 1 {
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let lop = LogicOp3::new_lut(&|x, y, _| x ^ y);
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b.lop2(lop, srcs[0], srcs[1])
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b.lop2(LogicOp2::Xor, srcs[0], srcs[1])
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} else if alu.get_src(0).bit_size() == 64 {
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b.isetp64(IntCmpType::I32, IntCmpOp::Ne, srcs[0], srcs[1])
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} else {
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@ -882,28 +878,21 @@ impl<'a> ShaderFromNir<'a> {
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}
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}
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nir_op_inot => {
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let lop = LogicOp3::new_lut(&|x, _, _| !x);
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if alu.def.bit_size() == 1 {
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b.lop2(lop, srcs[0], true.into())
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b.lop2(LogicOp2::PassB, true.into(), srcs[0].bnot())
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} else {
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assert!(alu.def.bit_size() == 32);
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b.lop2(lop, srcs[0], 0.into())
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b.lop2(LogicOp2::PassB, 0.into(), srcs[0].bnot())
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}
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}
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nir_op_ior => {
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b.lop2(LogicOp3::new_lut(&|x, y, _| x | y), srcs[0], srcs[1])
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}
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nir_op_ior => b.lop2(LogicOp2::Or, srcs[0], srcs[1]),
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nir_op_ishl => {
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let x = *srcs[0].as_ssa().unwrap();
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let shift = srcs[1];
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if alu.def.bit_size() == 64 {
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// For 64-bit shifts, we have to use clamp mode so we need
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// to mask the shift in order satisfy NIR semantics.
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let shift = b.lop2(
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LogicOp3::new_lut(&|x, y, _| x & y),
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shift,
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0x3f.into(),
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);
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let shift = b.lop2(LogicOp2::And, shift, 0x3f.into());
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let dst = b.alloc_ssa(RegFile::GPR, 2);
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b.push_op(OpShf {
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dst: dst[0].into(),
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@ -948,11 +937,7 @@ impl<'a> ShaderFromNir<'a> {
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if alu.def.bit_size() == 64 {
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// For 64-bit shifts, we have to use clamp mode so we need
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// to mask the shift in order satisfy NIR semantics.
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let shift = b.lop2(
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LogicOp3::new_lut(&|x, y, _| x & y),
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shift,
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0x3f.into(),
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);
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let shift = b.lop2(LogicOp2::And, shift, 0x3f.into());
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let dst = b.alloc_ssa(RegFile::GPR, 2);
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b.push_op(OpShf {
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dst: dst[0].into(),
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@ -991,9 +976,7 @@ impl<'a> ShaderFromNir<'a> {
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dst
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}
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}
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nir_op_ixor => {
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b.lop2(LogicOp3::new_lut(&|x, y, _| x ^ y), srcs[0], srcs[1])
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}
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nir_op_ixor => b.lop2(LogicOp2::Xor, srcs[0], srcs[1]),
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nir_op_pack_half_2x16_split => {
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assert!(alu.get_src(0).bit_size() == 32);
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let low = b.alloc_ssa(RegFile::GPR, 1);
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@ -1163,11 +1146,7 @@ impl<'a> ShaderFromNir<'a> {
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if alu.def.bit_size() == 64 {
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// For 64-bit shifts, we have to use clamp mode so we need
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// to mask the shift in order satisfy NIR semantics.
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let shift = b.lop2(
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LogicOp3::new_lut(&|x, y, _| x & y),
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shift,
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0x3f.into(),
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);
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let shift = b.lop2(LogicOp2::And, shift, 0x3f.into());
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let dst = b.alloc_ssa(RegFile::GPR, 2);
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b.push_op(OpShf {
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dst: dst[0].into(),
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@ -1452,6 +1452,36 @@ impl fmt::Display for IntCmpType {
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}
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}
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#[derive(Clone, Copy, Eq, Hash, PartialEq)]
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pub enum LogicOp2 {
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And,
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Or,
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Xor,
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PassB,
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}
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impl fmt::Display for LogicOp2 {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match self {
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LogicOp2::And => write!(f, "and"),
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LogicOp2::Or => write!(f, "or"),
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LogicOp2::Xor => write!(f, "xor"),
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LogicOp2::PassB => write!(f, "pass_b"),
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}
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}
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}
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impl LogicOp2 {
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pub fn to_lut(self) -> LogicOp3 {
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match self {
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LogicOp2::And => LogicOp3::new_lut(&|x, y, _| x & y),
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LogicOp2::Or => LogicOp3::new_lut(&|x, y, _| x | y),
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LogicOp2::Xor => LogicOp3::new_lut(&|x, y, _| x ^ y),
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LogicOp2::PassB => LogicOp3::new_lut(&|_, b, _| b),
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}
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}
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}
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#[derive(Clone, Copy, Eq, Hash, PartialEq)]
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pub struct LogicOp3 {
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pub lut: u8,
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@ -2597,6 +2627,23 @@ impl DisplayOp for OpISetP {
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}
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impl_display_for_op!(OpISetP);
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpLop2 {
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pub dst: Dst,
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#[src_type(ALU)]
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pub srcs: [Src; 2],
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pub op: LogicOp2,
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}
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impl DisplayOp for OpLop2 {
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fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(f, "lop2.{} {} {}", self.op, self.srcs[0], self.srcs[1],)
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}
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}
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpLop3 {
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@ -2997,6 +3044,27 @@ impl DisplayOp for OpPLop3 {
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}
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impl_display_for_op!(OpPLop3);
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpPSetP {
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pub dsts: [Dst; 2],
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pub ops: [PredSetOp; 2],
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#[src_type(Pred)]
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pub srcs: [Src; 3],
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}
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impl DisplayOp for OpPSetP {
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fn fmt_op(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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write!(
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f,
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"psetp{}{} {} {} {}",
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self.ops[0], self.ops[1], self.srcs[0], self.srcs[1], self.srcs[2],
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)
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}
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}
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#[repr(C)]
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#[derive(SrcsAsSlice, DstsAsSlice)]
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pub struct OpPopC {
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@ -4346,6 +4414,7 @@ pub enum Op {
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IMad64(OpIMad64),
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IMnMx(OpIMnMx),
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ISetP(OpISetP),
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Lop2(OpLop2),
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Lop3(OpLop3),
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PopC(OpPopC),
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Shf(OpShf),
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@ -4358,6 +4427,7 @@ pub enum Op {
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Sel(OpSel),
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||||
Shfl(OpShfl),
|
||||
PLop3(OpPLop3),
|
||||
PSetP(OpPSetP),
|
||||
Tex(OpTex),
|
||||
Tld(OpTld),
|
||||
Tld4(OpTld4),
|
||||
|
|
@ -4779,6 +4849,7 @@ impl Instr {
|
|||
| Op::IMad64(_)
|
||||
| Op::IMnMx(_)
|
||||
| Op::ISetP(_)
|
||||
| Op::Lop2(_)
|
||||
| Op::Lop3(_)
|
||||
| Op::Shf(_) => true,
|
||||
|
||||
|
|
@ -4790,7 +4861,7 @@ impl Instr {
|
|||
Op::Shfl(_) => false,
|
||||
|
||||
// Predicate ops
|
||||
Op::PLop3(_) => true,
|
||||
Op::PLop3(_) | Op::PSetP(_) => true,
|
||||
|
||||
// Texture ops
|
||||
Op::Tex(_)
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ impl LowerCopySwap {
|
|||
SrcRef::True => {
|
||||
b.lop2_to(
|
||||
copy.dst,
|
||||
LogicOp3::new_const(true),
|
||||
LogicOp2::PassB,
|
||||
Src::new_imm_bool(true),
|
||||
Src::new_imm_bool(true),
|
||||
);
|
||||
|
|
@ -85,18 +85,18 @@ impl LowerCopySwap {
|
|||
SrcRef::False => {
|
||||
b.lop2_to(
|
||||
copy.dst,
|
||||
LogicOp3::new_const(false),
|
||||
Src::new_imm_bool(true),
|
||||
LogicOp2::PassB,
|
||||
Src::new_imm_bool(true),
|
||||
Src::new_imm_bool(false),
|
||||
);
|
||||
}
|
||||
SrcRef::Reg(src_reg) => match src_reg.file() {
|
||||
RegFile::Pred => {
|
||||
b.lop2_to(
|
||||
copy.dst,
|
||||
LogicOp3::new_lut(&|x, _, _| x),
|
||||
copy.src,
|
||||
LogicOp2::PassB,
|
||||
Src::new_imm_bool(true),
|
||||
copy.src,
|
||||
);
|
||||
}
|
||||
_ => panic!("Cannot copy to Pred"),
|
||||
|
|
@ -157,6 +157,7 @@ impl LowerCopySwap {
|
|||
if x == y {
|
||||
/* Nothing to do */
|
||||
} else if x.is_predicate() {
|
||||
// TODO: Transform this in PLOP2 for SM5x-SM6x
|
||||
b.push_op(OpPLop3 {
|
||||
dsts: [x.into(), y.into()],
|
||||
srcs: [x.into(), y.into(), Src::new_imm_bool(true)],
|
||||
|
|
@ -166,10 +167,9 @@ impl LowerCopySwap {
|
|||
],
|
||||
});
|
||||
} else {
|
||||
let xor = LogicOp3::new_lut(&|x, y, _| x ^ y);
|
||||
b.lop2_to(x.into(), xor, x.into(), y.into());
|
||||
b.lop2_to(y.into(), xor, x.into(), y.into());
|
||||
b.lop2_to(x.into(), xor, x.into(), y.into());
|
||||
b.lop2_to(x.into(), LogicOp2::Xor, x.into(), y.into());
|
||||
b.lop2_to(y.into(), LogicOp2::Xor, x.into(), y.into());
|
||||
b.lop2_to(x.into(), LogicOp2::Xor, x.into(), y.into());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue