Commit graph

150544 commits

Author SHA1 Message Date
Samuel Pitoiset
53ca85ac2a radv,drirc: move RADV workarounds to 00-radv-defaults.conf
Because we have to maintain two different packages of Mesa, one
specific to RADV and another one for RadeonSI and such, it's a bit
annoying to have to synchronize the drirc entries. Currently, only our
Mesa package installs 00-mesa-defaults.conf which means we have to
backport the drirc RADV changes.

This splits 00-mesa-defaults.conf in two to move the drirc RADV entries
to src/amd/vulkan/00-radv-defaults.conf. Meson will install the file
only if RADV is built.

There is still a caveat for common drirc workarounds like for WSI but
they are rare enough and we could still duplicate them if needed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15152>
2022-02-25 15:05:56 +01:00
Timur Kristóf
1ca6b2f216 aco: Support memory modes properly with load/store_buffer_amd.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15161>
2022-02-25 14:08:39 +01:00
Timur Kristóf
ba4b48e787 aco: Support task_payload with barriers, refactor allowed storage class.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15161>
2022-02-25 14:08:36 +01:00
Timur Kristóf
cd0dd5d6b7 aco: Add storage class for Task Shader payload.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15161>
2022-02-25 13:20:08 +01:00
Timur Kristóf
962b2fe214 spirv: Use task_payload mode for generic task outputs and mesh inputs.
This new mode will be only used for the actual payload variables and
not the number of launched mesh shader workgroups, which will still
be treated as an output.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14930>
2022-02-25 06:52:07 +00:00
Timur Kristóf
f629fbd778 nir: Add new variable mode for task/mesh payload.
Task shader outputs work differently than other shaders, so they
need special consideration. Essentially, they have two kinds of
outputs:

1. Number of mesh shader workgroups to launch.
Will be still represented by a shader output.

2. Optional payload of up to (at least) 16K bytes.
These payload variables behave similarly to shared memory, but
the spec doesn't actually define them as shared memory (also, they
may be implemented differently by each backend), so we need to add
a new NIR variable mode for them.

These payload variables can't be represented by shader outputs
because the 16K bytes don't fit the 32x vec4 model that NIR uses
for its output variables.

This patch adds a new NIR variable mode: nir_var_mem_task_payload
and corresponding explicit I/O intrinsics, as well as support for
this new mode in nir_lower_io.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14930>
2022-02-25 06:52:07 +00:00
Timur Kristóf
d2d6eca081 radv: Refactor mesh shader draws and add num_workgroups.
Several of the new draw packets need this argument
including all of the taskmesh commands, so it's
best to always declare it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
bf519a7d47 ac/nir: Refactor mesh shader output code to smaller functions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
a84789f795 ac/nir: Make sure to exclude special outputs from arrayed output masks.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
3956c03b05 ac/nir: Sanitize mesh shader primitive indices using umin.
This makes our implementation friendlier to potentially buggy shaders,
meaning that it will less likely to hang the GPU.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
0746b98f4a ac/nir: Properly handle when mesh API workgroup size is smaller than HW.
The problem is that the real workgroup launched on NGG HW
can be larger than the size specified by the API, and the
extra waves need to keep up with barriers in the API waves.

There are 2 different cases:

1. The whole API workgroup fits in a single wave.
   We can shrink the barriers to subgroup scope and
   don't need to insert any extra ones.

2. The API workgroup occupies multiple waves, but not
   all. In this case, we emit code that consumes every
   barrier on the extra waves.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
d88516a23f ac/nir: Move LDS area for primitive count to the beginning.
This makes it impossible for out of bounds vertex and primitive
attribute stores and indices stores to overwrite this.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
9cc9cf77a8 aco: Fix multiview view index for mesh shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
082b691141 aco: Fix workgroup_id.y and .z for NV_mesh_shader.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
10ebfb3bf2 aco: Allow 1-byte loads and stores with load/store_buffer_amd
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Timur Kristóf
1ee3d49e3e radv: Better exclude special MS outputs from driver location assignment.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15034>
2022-02-25 06:31:33 +00:00
Guilherme Gallo
d1c6185b5a ci: skqp: Add Vulkan support for a630_skqp job
This commit adds support for Vulkan backend on a630_skqp job.

= Needed changes
- Needed to install libvulkan-dev package on system
- Refactored the way the available skqp reports are printed
  tested in development builds with skia tools

Piglit expectations had to be updated in various drivers due to !14750 not
having bumped the tags when it tried to uprev.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14686>
2022-02-25 05:50:06 +00:00
Guilherme Gallo
8bfef8bf6b ci: skqp: Build skqp from android-cts-10.0_r11 tag with Clang
The Android CTS 10 version is relative old when compared with skia main
branch, which was being used before. Some modifications in the skqp
build/runner scripts were needed to make it run on CI.

- skqp versions from android-cts have already all assets inside
  platform_tools folder.
  - along with the assets, are the render and unit files which are
    expected to pass in the Android CTS execution.
  - removed custom test files from the a630 folder, to make it comply
    with the CTS expectations.
- include new patches to remove Python2 dependencies and avoid the
  installation of it in rootfs.
- strip binariesthe built binaries `skqp` and `list_gpu_unit_tests`, as
  `is_debug = false` gn argument did not work, maybe it is not well
      tested in development builds with skia tools
- use Clang instead of GCC. The GCC support is not so graceful as it is
  in the skia main branch, some NEON instructions needs to be turned off
  in the GCC compilation, causing different tests result. This change
  does not imply a bigger rootfs, since the built skqp binary uses GCC
  libc++ and other library runtimes. So clang is just a build
  dependency.

= Changes in skqp results =

Some errors were found for GL backend and unit tests. GLES and VK tests are green.
All the failed tests were classified as expected to fail in the render and unit tests list.

```
gl_blur2rectsnonninepatch
gl_bug339297_as_clip
gl_bug6083
gl_dashtextcaps
```

```
SRGBReadWritePixels (../../tests/SRGBReadWritePixelsTest.cpp:214	Could not create sRGB surface context. [OpenGL])
```

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14686>
2022-02-25 05:50:06 +00:00
Mike Blumenkrantz
5ffed2a299 features: VK_EXT_depth_clip_control for lavapipe
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15126>
2022-02-25 05:27:27 +00:00
Mike Blumenkrantz
07c0801e60 lavapipe: EXT_depth_clip_control
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15126>
2022-02-25 05:27:27 +00:00
Emma Anholt
f458c7f200 ci/zink: Add testing of dEQP GLES3.1/3.2.
I think this has been kind of just an oversight.  Increases runtime by a
minute, to 5:30.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15159>
2022-02-24 16:16:57 -08:00
Emma Anholt
b4132bd026 ci/zink: Move testing to shared 64-core runners at Google.
Now the main deqp and piglit run takes about 4:30 of runner time in a
single job.

Added a couple of flakes that hit this MR, but which I think predate it
(probably due to not having #zink-ci until recently).

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15159>
2022-02-24 16:15:56 -08:00
Erik Faye-Lund
834db3aa8d docs: remove incorrect drivers from extension
This extension isn't wired up in Gallium, so there's just no way a
Gallium driver like Panfrost exposes it.

While there were support in i965 for this for the cancelled Broxton GPU,
thre's no such support in the Iris driver. And since Broxton has been
cancelled, it's unlikely to be wired up any time soon.

Fixes: da23a31726 ("docs/features: Update ASTC entries for Panfrost")
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15145>
2022-02-24 23:25:56 +00:00
Alyssa Rosenzweig
988d5aae74 panfrost: Flush resources when shadowing
When we shadow a resource, the backing BO is changed; as such,
existing references to the resource become invalid. So batches accessing the
resource need to be flushed (or otherwise have their references invalidated).

The wrong behaviour change (not flushing) was introduced when we started
tracking resources instead of BOs. The issue manifested as a severe performance
regression in glmark2's -bbuffer test, particular the subdata subtest. The issue
is magnified on slow CPUs; without the fix, the test becomes completely CPU
bound

Relevant glmark2 -bbuffer test from 43fps to 84fps.

Apparently, this causes functional issues too -- this performance-minded change
also fixes a few piglits.

Fixes: cecb889481 ("panfrost: Do tracking of resources, not BOs")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Chris Healy <cphealy@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13502>
2022-02-24 23:11:20 +00:00
Alyssa Rosenzweig
5536852d60 panfrost: Handle NULL samplers
Fixes a NULL dereference in Piglit fp-fragment-position, getting the
test to pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
2022-02-24 22:48:30 +00:00
Alyssa Rosenzweig
53ef20f08d panfrost: Handle NULL sampler views
Fixes a NULL dereference in Piglit fp-fragment-position.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
2022-02-24 22:48:30 +00:00
Alyssa Rosenzweig
304851422a panfrost: Fix set_sampler_views for big GL
Roughly use the freedreno logic to handle all the extra things that will
come up in our Piglit sooner than later.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
2022-02-24 22:48:30 +00:00
Alyssa Rosenzweig
4b2769493e panfrost/ci: Update xfails list
These tests seem to be passing now.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
2022-02-24 22:48:30 +00:00
Kenneth Graunke
97f18d2929 blorp: Add blorp_measure hooks to the blitter codepaths
I had missed these when hooking up the original support.

Fixes: 31eeb72e45 ("blorp: Add support for blorp_copy via XY_BLOCK_COPY_BLT")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15157>
2022-02-24 21:42:16 +00:00
Kenneth Graunke
e6b7e74308 iris: Set MI_FLUSH_DW::PostSyncOperation correctly
The MI_FLUSH_DW post-sync operation uses the same encoding as the
PIPE_CONTROL one so we can use the same helper.  Write PS Depth Count
is not supported, of course, as the blitter has no depth pipeline.

This means that we can write the timestamp register from the blitter.

Fixes: 604d97671b ("iris: Add support for flushing the blitter (hackily)")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15157>
2022-02-24 21:42:16 +00:00
Pavel Ondračka
c393753daa r300: add predicate instructions to statistics of vertex shaders
All of IF, ELSE, ENDIF, BREAK and CONTINUE were already translated
to the predication instructions in rc_vert_fc so all the flow control
we count at the moment is just BGNLOOP and ENDLOOP.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
2022-02-24 21:31:03 +00:00
Pavel Ondračka
8eb9bffdfc r300: report number of loops in shader statistics
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
2022-02-24 21:31:03 +00:00
Pavel Ondračka
517b37a08c r300: use %u specifiers when printing unsigned stats values
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6019
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
2022-02-24 21:31:03 +00:00
Pavel Ondračka
e7978412c3 r300: only print shader statistics when compilation succeeds
This allows to disregard the huge shaders that won't run anyway
and hopefully make catching shader regressions that result in a
compile failure easier.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
2022-02-24 21:31:03 +00:00
Mike Blumenkrantz
b124f83bc2 zink: add a flake channel
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15129>
2022-02-24 20:13:53 +00:00
Alyssa Rosenzweig
cd2a4cc47c pan/bi: Unit test message preloading optimization
To make sure it is applied in the cases we expect it to be, to avoid code
generation regressions. Functional regressions are expected to be caught by
integration-testing, so that is not focused on here.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 14:13:21 -05:00
Alyssa Rosenzweig
eb1479bda2 pan/bi: Support message preloading
Preload LD_VAR_IMM or VAR_TEX instructions in the first block of fragment
shaders on v7. Preloaded messages write to fixed registers; when replacing
instructions we insert moves from the registers at the start of the program and
hope coalescing goes to town. (Admittedly we don't do any coalescing yet...)
The extra moves hurts instruction count in some cases; the win for cycle count
should cancel this out. When we get smarter copy prop or RA, those moves should
go away anyway.

This optimization may hurt register pressure by extending the lifetime of up to
eight registers written in the first block. This is expected to be acceptable:
on a large shader-db, there are no additional spills/fills, and only two shaders
are hurt on thread count.

This optimization only applies to v7, as the hardware was not introduced on v6
and was removed for Valhall.

total instructions in shared programs: 2451624 -> 2454286 (0.11%)
instructions in affected programs: 909046 -> 911708 (0.29%)
helped: 4719
HURT: 3341
helped stats (abs) min: 1.0 max: 10.0 x̄: 1.49 x̃: 1
helped stats (rel) min: 0.08% max: 33.33% x̄: 6.79% x̃: 3.92%
HURT stats (abs)   min: 1.0 max: 50.0 x̄: 2.90 x̃: 2
HURT stats (rel)   min: 0.12% max: 66.67% x̄: 6.39% x̃: 3.45%
95% mean confidence interval for instructions value: 0.27 0.39
95% mean confidence interval for instructions %-change: -1.55% -1.11%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).

total tuples in shared programs: 1969529 -> 1963429 (-0.31%)
tuples in affected programs: 601327 -> 595227 (-1.01%)
helped: 5907
HURT: 1297
helped stats (abs) min: 1.0 max: 8.0 x̄: 1.41 x̃: 1
helped stats (rel) min: 0.07% max: 33.33% x̄: 7.25% x̃: 5.26%
HURT stats (abs)   min: 1.0 max: 40.0 x̄: 1.73 x̃: 1
HURT stats (rel)   min: 0.16% max: 31.75% x̄: 3.38% x̃: 2.02%
95% mean confidence interval for tuples value: -0.88 -0.81
95% mean confidence interval for tuples %-change: -5.52% -5.15%
Tuples are helped.

total clauses in shared programs: 401689 -> 387830 (-3.45%)
clauses in affected programs: 136944 -> 123085 (-10.12%)
helped: 8427
HURT: 4
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.65 x̃: 2
helped stats (rel) min: 0.49% max: 50.00% x̄: 19.88% x̃: 18.18%
HURT stats (abs)   min: 1.0 max: 4.0 x̄: 2.50 x̃: 2
HURT stats (rel)   min: 1.96% max: 19.05% x̄: 14.18% x̃: 17.86%
95% mean confidence interval for clauses value: -1.66 -1.63
95% mean confidence interval for clauses %-change: -20.15% -19.58%
Clauses are helped.

total cycles in shared programs: 202735.83 -> 201862.21 (-0.43%)
cycles in affected programs: 16295.46 -> 15421.83 (-5.36%)
helped: 3349
HURT: 1962
helped stats (abs) min: 0.041665999999999315 max: 1.0 x̄: 0.32 x̃: 0
helped stats (rel) min: 0.24% max: 100.00% x̄: 40.77% x̃: 33.33%
HURT stats (abs)   min: 0.041665999999999315 max: 1.5833329999999997 x̄: 0.10 x̃: 0
HURT stats (rel)   min: 0.09% max: 31.40% x̄: 2.95% x̃: 1.94%
95% mean confidence interval for cycles value: -0.17 -0.16
95% mean confidence interval for cycles %-change: -25.48% -23.76%
Cycles are helped.

total arith in shared programs: 74665.50 -> 74920.00 (0.34%)
arith in affected programs: 16059.92 -> 16314.42 (1.58%)
helped: 860
HURT: 3409
helped stats (abs) min: 0.041665999999999315 max: 0.25 x̄: 0.06 x̃: 0
helped stats (rel) min: 0.24% max: 37.50% x̄: 4.73% x̃: 2.56%
HURT stats (abs)   min: 0.041665999999999315 max: 1.5833329999999997 x̄: 0.09 x̃: 0
HURT stats (rel)   min: 0.09% max: 100.00% x̄: 8.99% x̃: 4.21%
95% mean confidence interval for arith value: 0.06 0.06
95% mean confidence interval for arith %-change: 5.83% 6.62%
Arith are HURT.

total texture in shared programs: 13083.50 -> 11877 (-9.22%)
texture in affected programs: 1663 -> 456.50 (-72.55%)
helped: 2377
HURT: 3
helped stats (abs) min: 0.5 max: 1.0 x̄: 0.51 x̃: 0
helped stats (rel) min: 6.25% max: 100.00% x̄: 87.12% x̃: 100.00%
HURT stats (abs)   min: 0.5 max: 0.5 x̄: 0.50 x̃: 0
HURT stats (rel)   min: 0.00% max: 25.00% x̄: 16.67% x̃: 25.00%
95% mean confidence interval for texture value: -0.51 -0.50
95% mean confidence interval for texture %-change: -87.98% -86.00%
Texture are helped.

total vary in shared programs: 10220.62 -> 4183.88 (-59.06%)
vary in affected programs: 10126.50 -> 4089.75 (-59.61%)
helped: 8538
HURT: 0
helped stats (abs) min: 0.125 max: 1.0 x̄: 0.71 x̃: 0
helped stats (rel) min: 7.14% max: 100.00% x̄: 74.74% x̃: 87.50%
95% mean confidence interval for vary value: -0.71 -0.70
95% mean confidence interval for vary %-change: -75.32% -74.16%
Vary are helped.

total quadwords in shared programs: 1766717 -> 1757161 (-0.54%)
quadwords in affected programs: 553801 -> 544245 (-1.73%)
helped: 6760
HURT: 711
helped stats (abs) min: 1.0 max: 11.0 x̄: 1.58 x̃: 1
helped stats (rel) min: 0.09% max: 29.41% x̄: 5.31% x̃: 4.84%
HURT stats (abs)   min: 1.0 max: 33.0 x̄: 1.54 x̃: 1
HURT stats (rel)   min: 0.10% max: 31.13% x̄: 2.53% x̃: 1.61%
95% mean confidence interval for quadwords value: -1.31 -1.25
95% mean confidence interval for quadwords %-change: -4.67% -4.46%
Quadwords are helped.

total threads in shared programs: 52899 -> 52897 (<.01%)
threads in affected programs: 4 -> 2 (-50.00%)
helped: 0
HURT: 2

total preloads in shared programs: 0 -> 116492
preloads in affected programs: 0 -> 116492
helped: 0
HURT: 8604
HURT stats (abs)   min: 2.0 max: 24.0 x̄: 13.54 x̃: 14
HURT stats (rel)   min: 0.00% max: 0.00% x̄: 0.00% x̃: 0.00%
95% mean confidence interval for preloads value: 13.45 13.63
95% mean confidence interval for preloads %-change: 0.00% 0.00%
Preloads are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 14:09:14 -05:00
Alyssa Rosenzweig
c8437cd415 pan/bi: Account for message preloading in shaderdb
If a message-passing instruction like LD_VAR is preloaded, it will no longer be
counted in the shader cycle counts. Add a special message preload counter that
approximates the cost of preloading, so this information doesn't get a lost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 12:51:04 -05:00
Alyssa Rosenzweig
19541dc8c8 pan/bi: Add bi_before_nonempty_block helper
To be used in the message preloading pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 12:51:04 -05:00
Alyssa Rosenzweig
6618697e0e panfrost: Pack message preloads from compiler
Include full message preload descriptors in the RSD on v7, and do the obvious
packing for fragment shader message preloads.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 12:51:04 -05:00
Alyssa Rosenzweig
bd06a26662 panfrost: Add an unpacked message preload struct
The compiler will soon produce preloaded messages, but it should not pack them
itself, as this would require depending on GenXML or handcoding bitfields / bit
packs in the compiler. Instead, add a struct encoding the unpacked form of the
message, used as ABI between the compiler and the common driver.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 12:51:04 -05:00
Alyssa Rosenzweig
2d0c4973dc panfrost: Remove Message Preload Descriptor from v6.xml
It is an anachronism, as this descriptor was added in v7 and, seemingly, removed
immediately after. Good work.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
2022-02-24 12:50:58 -05:00
Igor Torrente
b130f8f4cf venus: add macros to help with future extensions
Currently we have to add almost the same code to the
`vn_physical_device_init_{features, properties}` to add
the extension to the `physical_dev->{features, properties}`
list.

These macros improves the code reusage.

Signed-off-by: Igor Torrente <igor.torrente@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15059>
2022-02-24 15:55:57 +00:00
Alyssa Rosenzweig
43bbe367ea panfrost/ci: Move T860 flake to skip
Actually an xfail but occassionally passes and gives us no new information, only
noise.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-and-acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15154>
2022-02-24 14:51:31 +00:00
Alyssa Rosenzweig
5c07f7c427 panfrost/ci: Move T720 flakes to skips
Doesn't seem like these will be resolved anytime soon..

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-and-acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15154>
2022-02-24 14:51:31 +00:00
Tomeu Vizoso
eecc62ccbd Revert "ci: Disable jobs to the Collabora lab"
This reverts commit f692bda484.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15153>
2022-02-24 13:44:09 +01:00
Iago Toral Quiroga
cf99584f51 broadcom/compiler: move uniforms right before their first use after scheduling
On V3D the quality of the code we generate is significantly affected by
how we decide to assign accumulators during register allocation, which
is determined by liveness, favoring short-lived temps.

There are many shaders that end up doing a whole lot of uniform loads
first, and using them later, which is very inconvenient for our register
allocation process because this increases uniform liveness and causes
us to use accumulators less efficientely, leading to significant churn.

To fix this, we move uniforms right before their first use in the same
block, but we need to do this after NIR scheduling, which means we are
doing it in non-SSA form, since the scheduler has a tendency to undo
this optimization and it is not easy to modify it to avoid it, since it
works in more abstract terms, using instruction dependencies, estimated
register pressure and instruction delay information to do its work,
which are very different concepts.

total instructions in shared programs: 13316738 -> 13033613 (-2.13%)
instructions in affected programs: 10389172 -> 10106047 (-2.73%)
helped: 55442
HURT: 16144

total threads in shared programs: 413722 -> 415048 (0.32%)
threads in affected programs: 1428 -> 2754 (92.86%)
helped: 680
HURT: 17

total loops in shared programs: 1716 -> 1690 (-1.52%)
loops in affected programs: 26 -> 0
helped: 26
HURT: 0

total uniforms in shared programs: 3704313 -> 3705181 (0.02%)
uniforms in affected programs: 687730 -> 688598 (0.13%)
helped: 2920
HURT: 7384

total max-temps in shared programs: 2364785 -> 2175190 (-8.02%)
max-temps in affected programs: 1215387 -> 1025792 (-15.60%)
helped: 49667
HURT: 1556

total spills in shared programs: 4241 -> 4248 (0.17%)
spills in affected programs: 642 -> 649 (1.09%)
helped: 11
HURT: 19

total fills in shared programs: 6115 -> 6125 (0.16%)
fills in affected programs: 1276 -> 1286 (0.78%)
helped: 11
HURT: 21

total sfu-stalls in shared programs: 34381 -> 36578 (6.39%)
sfu-stalls in affected programs: 16055 -> 18252 (13.68%)
helped: 3647
HURT: 5206

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
2022-02-24 11:36:00 +00:00
Iago Toral Quiroga
f1d20ec67c nir/nir_opt_move: handle non-SSA defs
We just skip register defs and avoid moving register reads across them.
This allows us to run this pass in non-SSA form.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
2022-02-24 11:36:00 +00:00
Iago Toral Quiroga
fe2249eac5 nir: add a nir_instr_def_is_register helper
This returns true if the instruction has a dest that is not an SSA value.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
2022-02-24 11:36:00 +00:00
Iago Toral Quiroga
0a04468704 nir/nir_opt_move: allow to move uniform loads
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
2022-02-24 11:36:00 +00:00