Commit graph

58650 commits

Author SHA1 Message Date
Daniel Manjarres
4f33ded115 glx: Fix glxUseXFont for glxWindow and glxPixmaps
The current implementation of glxUseXFont requires creating
a temporary pixmap and graphics context, which requires a real
old-school X11 Window, not a glxDrawable. This patch changes
things so that glxUseXFont will also accept a glxWindow or
glxPixmap, and lookup the underlying X11 Drawable. Without
this patch glxUseXFont generates a giant stream of Xerrors
about bad drawables and bad graphics contexts.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54372

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 291be28476)
2014-10-19 18:38:19 +01:00
Kenneth Graunke
13a4fd2430 i965: Fix register write checks.
When mapping the buffer a second time, we need to use the new pointer,
not the one from the previous mapping.  Otherwise, we will most likely
crash.

Apparently, we've just been getting lucky and getting the same
bo->virtual pointer in both cases.  libdrm probably has a hand in that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 94841b6d5d)
2014-10-13 01:16:04 +01:00
Kenneth Graunke
5e6ee119c0 i965: Use BDW_MOCS_PTE for renderbuffers.
Write-back caching cannot be used for buffers being scanned out by the
display engine; surfaces used for scan-out must be write-through or
uncached.  I originally chose WT for render targets because it works in
all cases.  However, we really want to use write-back caching where
possible, as it is more efficient.

Most renderbuffers are not used for scanout - off-screen FBOs certainly
are fine, and non-pageflipped backbuffers should be fine as well.  So
in most cases WB will work.  However, we don't know what will be used
for scan-out, so we instead simply use the PTE value specified by the
kernel, as it knows these things.

This matches our MOCS choice on Haswell.

Fixes performance regressions since commit ee4484be3d
in a microbenchmark (spotted by Eero Tamminen).  Improves performance
in GLBenchmark 2.7/EgyptHD by 7.44362% +/- 0.496939% (n=55) on a
Broadwell GT2.  Improves performance in a bunch of other microbenchmarks
by ~15% or so.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit b7844d1248)
2014-10-13 01:15:58 +01:00
Kenneth Graunke
85d7eb730a i965: Add a BRW_MOCS_PTE #define.
Like BDW_MOCS_WB and BDW_MOCS_WT, this specifies that we want to use all
three caches (L3, LLC, and eLLC where available), but leaves the LLC
caching mode up to the kernel's page table entry.

This allows the kernel to pick WB/WT/UC based on whether it's using a
buffer for scanout.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d489a8a73d)
2014-10-13 01:15:32 +01:00
Michel Dänzer
64c2bdc334 r600g,radeonsi: Always use GTT again for PIPE_USAGE_STREAM buffers
Putting those in VRAM can cause long pauses due to buffers being moved
into / out of VRAM.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84662
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 7b4276d7ac)
2014-10-13 01:13:24 +01:00
Ilia Mirkin
125cd86cd4 gk110/ir: add dnz flag emission for fmul/fmad
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c74be01e80)
2014-10-13 01:13:00 +01:00
Ilia Mirkin
e3e68a36db gm107/ir: add dnz emission for fmul
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d58037ccf5)
2014-10-13 01:12:38 +01:00
Brian Paul
745a0bfd62 st/wgl: add WINAPI qualifiers on wgl function typedefs
Fixes a release build segfault when wglCreateContextAttribsARB()
calls the wglCreateContext() function.

Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matthew McClure <mcclurem@vmware.com>
(cherry picked from commit 90dc71b454)
2014-10-13 01:12:01 +01:00
Brian Paul
ada5fd6e85 mesa: fix spurious wglGetProcAddress / GL_INVALID_OPERATION error
On Windows, the Piglit primitive-restart test was failing a
glGetError()==0 assertion when it was run w/out any command line
arguments.  Piglit's all.py script only runs primitive-restart
with arguments so this case isn't normally hit during a full
piglit run.

The basic problem is Microsoft's opengl32.dll calls glFlush
from wglGetProcAddress() and Piglit uses wglGetProcAddress() to
resolve glPrimitiveRestartNV() which is called inside glBegin/End.
See comments in the code for more info.

Plus, improve the comments for _mesa_alloc_dispatch_table().

Cc: <mesa-stable@lists.freedesktop.org>
Acked-by: Sinclair Yeh <syeh@vmware.com>
(cherry picked from commit c7f0755caa)
2014-10-13 01:11:23 +01:00
Michel Dänzer
ecd2d078ac radeonsi: Clear sampler view flags when binding a buffer
Fixes assertion failure while running the Unreal Engine 4 Elemental demo:

.../si_blit.c:322:si_decompress_color_textures: Assertion `tex->cmask.size || tex->fmask.size' failed.

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit ed03747e6a)
2014-10-13 01:11:04 +01:00
Dave Airlie
08f7e3591d mesa: fix GetTexImage for 1D array depth textures
While running piglit in virgl, I hit an assert in intel driver.

"qemu-system-x86_64: intel_tex.c:219: intel_map_texture_image: Assertion `tex_image->TexObject->Target != 0x8C18 || h == 1' failed."

Thanks to Eric and Ken for pointing me in the right direction,

Fix the get_tex_depth to do the same fixup as get_tex_rgba does
for 1D array textures.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 8df3c02cdc)
2014-10-13 01:01:38 +01:00
Tomasz Figa
c90cd077bd st/mesa: Fix paths used in Android builds
With current makefiles the build fails because source and build paths
are generated incorrectly. With Android build system the top_srcdir and
top_builddir variables are undefined and all paths are relative to where
Android.mk is located. This ends up with path likes
external/mesa/src/mesa/src/mesa/ for both source and build paths, which
are obviously wrong.

This patch fixes this by overriding resulting SRCDIR and BUILDDIR
variables with empty string, so that paths end up being relative to
Android.mk file again. Appending correct build path to generated files
is already done in Android.gen.mk.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit b4ffd19e6c)
2014-10-03 01:28:02 +01:00
Tomasz Figa
dffbee6668 st/mesa: Generate format_info.c in Android builds
Current Android makefiles lack generation of format_info.c, which is
a dependency of main/format.c. This patch adds necessary code to
Android.gen.mk.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 98445fd25e)
2014-10-03 01:27:56 +01:00
Tomasz Figa
58ba481e8e util: Include in Android builds
This patch fixes Android build failures by including src/util directory
in compilation. Files inside of this directory are compiled into
libmesa_util static library and linked with resulting libGLES_mesa.

Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit d703abf735)
2014-10-03 01:27:50 +01:00
Keith Packard
ccf908e382 glx/dri3: Provide error diagnostics when DRI3 allocation fails
Instead of just segfaulting in the driver when a buffer allocation fails,
report error messages indicating what went wrong so that we can debug things.

As a simple example, chromium wraps Mesa in a sandbox which doesn't allow
access to most syscalls, including the ability to create shared memory
segments for fences. Before, you'd get a simple segfault in mesa and your 3D
acceleration would fail. Now you get:

$ chromium --disable-gpu-blacklist
[10618:10643:0930/200525:ERROR:nss_util.cc(856)] After loading Root Certs, loaded==false: NSS error code: -8018
libGL: pci id for fd 12: 8086:0a16, driver i965
libGL: OpenDriver: trying /local-miki/src/mesa/mesa/lib/i965_dri.so
libGL: Can't open configuration file /home/keithp/.drirc: Operation not permitted.
libGL: Can't open configuration file /home/keithp/.drirc: Operation not permitted.
libGL error: DRI3 Fence object allocation failure Operation not permitted
[10618:10618:0930/200525:ERROR:command_buffer_proxy_impl.cc(153)] Could not send GpuCommandBufferMsg_Initialize.
[10618:10618:0930/200525:ERROR:webgraphicscontext3d_command_buffer_impl.cc(236)] CommandBufferProxy::Initialize failed.
[10618:10618:0930/200525:ERROR:webgraphicscontext3d_command_buffer_impl.cc(256)] Failed to initialize command buffer.

This made it pretty easy to diagnose the problem in the referenced bug report.

Bugzilla: https://code.google.com/p/chromium/issues/detail?id=415681
Signed-off-by: Keith Packard <keithp@keithp.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 3202926746)
2014-10-03 01:27:42 +01:00
Thomas Hellstrom
ed440234d4 st/xa: Fix regression in xa_yuv_planar_blit()
Commit "st/xa: scissor to help tilers" broke xa_yuv_planar_blit() and vmwgfx
textured video. Fix this by implementing scissors also in the yuv draw path.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Cc: Rob Clark <robclark@freedesktop.org>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 46537f1d03)
2014-10-03 01:27:34 +01:00
Marek Olšák
d95520d297 st/dri: remove GALLIUM_MSAA and __GL_FSAA_MODE environment variables
Some users don't understand that these variables can break OpenGL.
The general is rule is that if an app supports MSAA, you mustn't use
GALLIUM_MSAA.

For example, if an app has an 8xMSAA FBO and GALLIUM_MSAA=4
is set, resolving the FBO to the back buffer will be rejected which will look
like this on all gallium drivers:

http://www.phoronix.com/scan.php?page=article&item=amd_radeonsi_msaa

The environment variables also have no effect on modern apps like TF2, but
there is still a performance hit due to wasted bandwidth and VRAM.

In a nutshell, it does more harm than good.

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 8449121971)
2014-09-28 20:52:02 +01:00
Ian Romanick
384816c6db glsl: Strip arrayness from ir_type_dereference_variable too
If the thing being dereferenced is a record or an array of records, it
should be treated as row-major.  The ir_type_derference_record path
already does this, and I think I intended to do the same for this path
in b17a4d5d.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83741
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit c3f17bb18f)
2014-09-27 18:56:39 +01:00
Ian Romanick
d556ed889d glsl: Round struct size up to at least 16 bytes
Per rule #9, the size of the structure is vec4 aligned.  The MAX2 in the
loop ensures that sizes >= 16 bytes are vec4 aligned.  The new MAX2
after the loop ensures that sizes < 16 bytes are vec4 aligned.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82932
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 2ab71e1486)
2014-09-27 18:56:39 +01:00
Ian Romanick
d9444533aa glsl: Make sure row-major array-of-structure get correct layout
Whether or not the field is row-major (because it might be a bvec2 or
something) does not affect the array itself.  We need to know whether an
array element in its entirety is row-major.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83506
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 5c75270c34)
2014-09-27 18:56:39 +01:00
Ian Romanick
9328440ef7 glsl: Make sure fields after small structs have correct padding
Previously the linker would correctly calculate the layout, but the
lower_ubo_reference pass would not apply correct alignment to fields
following small (less than 16-byte) nested structures.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83533
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8e01c66da6)
2014-09-27 18:56:39 +01:00
Michel Dänzer
1ac204121b st/mesa: Use PIPE_USAGE_STAGING for GL_STATIC/DYNAMIC/STREAM_READ buffers
Such buffers can only be useful by reading from them with the CPU, so we
need to make sure CPU reads are fast.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84178
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 7e55c3b352)
2014-09-27 18:56:39 +01:00
Ilia Mirkin
fef6059a81 gm107/ir: take relative pfetch offset into account
There is no dedicated instruction for this, so just combine it with the
constant offset.

Acked-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a5bbfeda97)
2014-09-27 18:56:38 +01:00
Ilia Mirkin
34809f8eef gm107/ir: add support for indirect const buffer selection
This was missed in the commit that enabled it for fermi/kepler as part
of ARB_gpu_shader5

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit cdc4de1215)
2014-09-27 18:56:38 +01:00
Ilia Mirkin
9a79018840 gm107/ir: fix texture argument order
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 0532a5fd00)
2014-09-27 18:56:38 +01:00
Ilia Mirkin
5aff846a60 gm107/ir: fix manual TXD for array targets
This parallels the fixes in commit afea9bae.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit d3c3bba6d0)
2014-09-27 18:56:38 +01:00
Ilia Mirkin
fb4e23626f nv50/ir: avoid deleting pseudo instructions too early
What happens is that a SPLIT operation is part of the spill node, and as
a pseudo op, the instruction gets erased after processing its first def.
However the later defs still need to refer to it, so instead delay
deleting until after that whole RA node is done processing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79462
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 0147c10c5f)
2014-09-27 18:56:38 +01:00
Kenneth Graunke
607d0b9578 mesa: Set correct array element in vbo_exec_vtx_init.
I'm not familiar with this code, but this sure appears to be a typo.
It looks like the intent is to set each array element, not arrays[0]
each time.  Notably, the loop just below uses "array", not "arrays".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit f81052dc9b)
2014-09-27 18:56:38 +01:00
Kenneth Graunke
4fce87bcee mesa: Use proper structure for glGet*(GL_TEXTURE_COORD_ARRAY*).
The code in get.c that handles this uses ctx->Array.VAO->VertexAttrib,
which is a gl_vertex_attrib_array structure, not a gl_client_array.

The offsets of all fields happened to be the same in both structures, at
least on x86_64.  "Size," "Type," and "Stride" are obviously the same:
both structures start with the same fields, in the same order.

"Enabled" is dicier: there are different fields before it in both
structures, including pointer sized values which might need special
alignment.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d0ec6e8509)
2014-09-27 18:56:37 +01:00
Marek Olšák
8e2d0f59f7 radeonsi: properly destroy the GS copy shader and scratch_bo for compute
Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit dc05a9e4e0)
[Emil Velikov: remove unref scratch_bo, s/si_shader/si_pipe_shader/]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-09-27 18:55:52 +01:00
Marek Olšák
4748d2f065 radeonsi: release GS rings at context destruction
Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 711623f7c8)
[Emil Velikov: s/ring/ring.buffer/]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-09-27 18:55:07 +01:00
Andreas Pokorny
f74bca93b4 i915: Fix black buffers when importing prime fds
Width and Height of the imported image was never initialized from the
imported bo.

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andreas Pokorny <andreas.pokorny@canonical.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit df341320c9)
2014-09-27 18:12:57 +01:00
Andreas Pokorny
ceebec140b egl/drm: expose KHR_image_pixmap extension
This changes enables EGL_KHR_image_pixmap in the egl drm platform, which is implemented
there but has not been advertised yet.

Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andreas Pokorny <andreas.pokorny@canonical.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
(cherry picked from commit 53b614bfd3)
2014-09-27 18:12:51 +01:00
Roland Scheidegger
095a6a0af1 gallivm: fix idiv
ffeb77c7b0 had a typo which turned all signed
integer divisions into unsigned ones. Oops.
This gets us back the 51 little piglits
(all from glsl built-in-functions, fs/vs/gs-op-div-int-ivec2 and similar).

Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
(cherry picked from commit 5e1fcc6258)
2014-09-27 18:12:44 +01:00
rconde
04a9d7d44a gallivm,tgsi: fix idiv by zero crash
While the result of signed integer division by zero is undefined by glsl
(and doesn't exist with d3d10), we must not crash, so need to make sure we
don't get sigfpe much like udiv already does.
Unlike udiv where we return 0xffffffff (as required by d3d10) there is
no requirement right now to return anything specific so we use zero.

(cherry picked from commit ffeb77c7b0)
Nominated-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83570
2014-09-23 00:52:51 +01:00
Tom Stellard
d4289fc37b clover: Add support to mem objects for multiple destructor callbacks v2
The spec says that mem objects should maintain a stack of callbacks
not just one.

v2:
  - Remove stray printf.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

CC: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c6d9801409)
2014-09-23 00:46:00 +01:00
Brian Paul
9599cd6a2f mesa: fix prog_optimize.c assertions triggered by SWZ opcode
The SWZ instruction can have swizzle terms >4 (SWIZZLE_ZERO, SWIZZLE_ONE).
These swizzle terms caused a few assertions to fail.
This started happening after the commit "mesa: Actually use the Mesa IR
optimizer for ARB programs." when replaying some apitrace files.

A new piglit test (tests/asmparsertest/shaders/ARBfp1.0/swz-08.txt)
exercises this.

Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit 7b2c703244)
2014-09-23 00:45:21 +01:00
Richard Sandiford
27f70a9273 swrast: Fix handling of MESA_FORMAT_L8A8_SRGB for big-endian
Luminance is the least-significant byte of the uint16, rather than the
lowest byte in memory.  Other parts of mesa already handle this correctly
for big-endian, and swrast already handles other MESA_FORMAT_x8y8 formats
correctly.  This case was just an odd-one-out.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ecc48f83c8)
2014-09-23 00:45:01 +01:00
Richard Sandiford
0a6e33ea74 mesa: Fix alpha component in unpack_R8G8B8X8_SRGB.
The function was using the "X" component as the alpha channel,
rather than setting alpha to 1.0.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3ff5c6a6c4)
2014-09-23 00:44:30 +01:00
Connor Abbott
e471841048 r300g: set register classes before interferences
In commit 567e2769b8 ("ra: make the p, q
test more efficient") I unknowingly introduced a new requirement to the
register allocator API: the user must set the register class of all
nodes before setting up their interferences, because
ra_add_conflict_list() now uses the classes of the two interfering
nodes. i965 already did this, but r300g was setting up register classes
interleaved with setting up the interference graph. This led to us
calculating the wrong q total, and in certain cases
e78a01d5e6 (" ra: optimistically color
only one node at a time") made it so that this bug caused a segfault. In
particular, the error occurred if the q total was decremented to 1 below
0 for the last node to be pushed onto the stack.  Since q_total is an
unsigned integer, it overflowed to 0xffffffff, which is what
lowest_q_total happens to be initialzed to. This means that we would
fail the "new_q_total < lowest_q_total" check on line 476 of
register_allocate.c, and so the node would never be pushed onto the
stack, which led to segfaults in ra_select() when we failed to ever give
it a register.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82828
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Pavel Ondračka <pavel.ondracka@email.cz>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
(cherry picked from commit afd82dcad1)
2014-09-16 22:18:34 +01:00
Gwenole Beauchesne
f86efb4285 i965: add support for RGBA dma_buf imports.
This allows for importing foreign buffers in RGB32 native endian
byte order, i.e. DRM_FORMAT_XBGR8888, and DRM_FORMAT_ABGR8888.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit e1c50abf8a)
2014-09-16 22:17:58 +01:00
Kenneth Graunke
84a58f462a i965: Mark delta_x/y as BAD_FILE if remapped away completely.
Commit afe3d1556f (i965: Stop doing
remapping of "special" regs.) stopped remapping delta_x/delta_y, and
additionally stopped considering them always-live.  We later realized
delta_x was used in register allocaiton, so we actually needed to remap
it, which was fixed in commit 23d782067a
(i965/fs: Keep track of the register that hold delta_x/delta_y.).

However, that commit didn't restore the "always consider it live" part.
If all the code using delta_x was eliminated, fs_visitor::delta_x would
be left pointing at its old register number.  Later code in register
allocation would handle that register number specially...even though it
wasn't actually delta_x.

To combat this, set delta_x/y to BAD_FILE if they're eliminated, and
check for that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83127
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 78bd126194)
2014-09-16 22:17:40 +01:00
Richard Sandiford
605734780e gallivm: Fix uses of 2^24
Fallback cases in lp_bld_arit.c used 2^24 to mean "2 to the power 24",
but in C it's "2 xor 24", i.e. 26.  Fixed by using 1<< instead.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 1a65629ccc)
2014-09-16 22:16:58 +01:00
Ilia Mirkin
efe8fc687d nouveau: change internal variables to avoid conflicts with macro args
Reported by Coverity

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit b13a4ca3f7)
2014-09-16 22:16:16 +01:00
Brian Paul
051543962f mesa: fix _mesa_free_pipeline_data() use-after-free bug
Unreference the ctx->_Shader object before we delete all the pipeline
objects in the hash table.  Before, ctx->_Shader could point to freed
memory when _mesa_reference_pipeline_object(ctx, &ctx->_Shader, NULL)
was called.

Fixes crash when exiting the piglit rendezvous_by_location test on
Windows.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 0d73ac6b02)
2014-09-16 22:15:29 +01:00
Andreas Boll
b92ea2a10d gallium/util: add missing u_debug include
Needed for assert.
Fixes build on BE archs with -Werror=implicit-function-declaration.

In file included from
../../../../../src/gallium/auxiliary/draw/draw_fs.c:30:0:
../../../../../src/gallium/auxiliary/util/u_math.h: In function
'util_memcpy_cpu_to_le32':
../../../../../src/gallium/auxiliary/util/u_math.h:810:4: error:
implicit declaration of function 'assert'
[-Werror=implicit-function-declaration]
    assert(n % 4 == 0);
        ^

Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 2a13ff954d)
2014-09-16 22:14:03 +01:00
Ilia Mirkin
b0131d951b nouveau: only enable stencil func if the visual has stencil bits
The _Enabled property already has the relevant information.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3c81de5851)
2014-09-16 22:13:45 +01:00
Ilia Mirkin
0c1f24b46c nouveau: only enable the depth test if there actually is a depth buffer
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 79959e5de5)
2014-09-16 22:13:00 +01:00
Maarten Lankhorst
a4d4ab929e nouveau: remove unneeded assert
No idea why it was added, but the code runs fine even on videos
where it triggers.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 8ab85bfcd5)
2014-09-16 22:08:48 +01:00
Maarten Lankhorst
2b43d48509 nouveau: rework reference frame handling
Fixes a regression from "nouveau/vdec: small fixes to h264 handling"

New picking order for frames:
 1. Vidbuf pointer matches.
 2. Take the first kicked ref.
 3. If that fails, take a ref that has a different last_used.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit a41aad8431)
2014-09-16 22:08:27 +01:00