Commit graph

31705 commits

Author SHA1 Message Date
Brian Paul
bf7a4f4441 svga: s/unsigned/enum tgsi_texture_type/
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-07-11 08:09:14 -06:00
Brian Paul
1d82674969 svga: s/unsigned/enum tgsi_swizzle
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-07-11 08:09:14 -06:00
Brian Paul
3effacf172 svga: s/unsigned/enum tgsi_interpolate_mode/
And s/unsigned/enum tgsi_interpolate_loc/

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-07-11 08:09:14 -06:00
Brian Paul
9330112b35 svga: s/unsigned/enum tgsi_file_type/
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-07-11 08:09:14 -06:00
Brian Paul
1b5e88becd svga: s/unsigned/enum tgsi_semantic/
Makes gdb debugging a little nicer.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-07-11 08:09:14 -06:00
Marek Olšák
aaee0d1bbf gallium: use "ull" number suffix to keep the QtCreator parser happy
It can't parse "llu".

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-07-10 22:44:48 +02:00
Brian Paul
3b28eaabf6 svga: fix PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE value
This query is supposed to return the max texture buffer size/width in
texels, not size in bytes.  Divide by 16 (the largest format size) to
return texels.

Fixes Piglit arb_texture_buffer_object-max-size test.

Cc: mesa-stable@lists.freedesktop.org

Reviewed-by :Charmaine Lee <charmainel@vmware.com>
2017-07-10 11:11:26 -06:00
Brian Paul
f8f71cb6f3 svga: fix breakage in create_backed_surface_view()
This fixes a regression in some piglit tests since commit 5e5d5f1a2e.
I think I mis-resolved the merge conflict when cherry-picking that
commit to master.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-07-10 11:11:26 -06:00
Ilia Mirkin
6c7b7aa3d8 a5xx: fix condition for updating *_FS_OUTPUT_CNTL
The register values depend on the currently set program, so make sure to
revalidate when the program changes.

Fixes glsl-1.10-fragdepth as well as
dEQP-GLES3.functional.shaders.fragdepth.compare.*

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-07-09 18:36:13 -04:00
Dave Airlie
edf2acbeb1 radv: add support for using addrlib max alignment.
Rather than using 64k, use what addrlib returns as the base
alignment for vulkan allocations.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-09 22:17:59 +01:00
Ilia Mirkin
ce3e2ec3b7 a5xx: remove no-longer-accurate border color layout comment
Better to just point at the bcolor_entry struct which has our current
understanding encoded into it. Also add an assert to ensure that the
struct remains the expected size.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-08 21:14:58 -04:00
Ilia Mirkin
4ad4009473 a5xx: fix border color for depth formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-08 21:14:58 -04:00
Ilia Mirkin
cf173b5dcd a5xx: add border color clamping, add packed border color formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-08 21:14:58 -04:00
Ilia Mirkin
a9b58a00bb a5xx: fix border colors for swizzled texture formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-08 21:14:58 -04:00
Ilia Mirkin
a4eeb0c403 a5xx: fix integer texture border colors
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-08 21:14:58 -04:00
Ilia Mirkin
1acc101b3f a5xx: fix primitive restart
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-08 21:14:58 -04:00
Roland Scheidegger
4db72852a1 draw: handle more TGSI_SEMANTIC_COLOR indices
It could only handle indices 0/1, otherwise what happened was bad (accessing
array out of bounds, no crash but kind of random). This is enough for the gl
state tracker (primary/secondary color) but not enough for some other state
trackers (d3d9 has no limits on the number of color interpolants).
The complexity with color semantics are all due to the front/back mapping (2
outputs in the vs map to one input in the fs) so this isn't extended to
indices > 1 - d3d9 has no use for back colors, therefore this isn't needed and
still only 2 back colors can be handled correctly.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-07-08 06:02:18 +02:00
Brian Paul
5b8d33acef svga: adjust line subpixel position for HWv8
This fixes two regressions on HWv8:
  Piglit gl-1.0-ortho-pos
  Piglit/glean fbo
This was caused by commit c2b92dada0 "svga: clamp device line width
to at least 1 to fix HWv8 line stippling"

This also fixes two conform tests: Vertex Order and Polygon Face

No Piglit/conform changes with HWv9 or later.

VMware bug 1905053

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-07-07 12:04:17 -06:00
Aleksander Morgado
5d8514de14 etnaviv: fix refcnt initialization in etna_screen
Despite being a member of the etna_screen struct, 'refcnt' is used by
the winsys-specific logic to track the reference count of the object
managed in a hash table. When the count reaches zero, the pipe screen
is removed from the table and destroyed.

Fix the logic by initializing the refcnt to 1 when screen created.
This initialization is done in etna_screen_create(), to follow the
same logic as in freedreno and virgl.

Fixes: c9e8b49b88 ("etnaviv: gallium driver for Vivante GPUs")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Aleksander Morgado <aleksander@aleksander.es>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2017-07-07 15:39:29 +02:00
Ilia Mirkin
c036122646 a5xx: add support for rendering to RGB10A2_UNORM formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-07 09:09:48 -04:00
Ilia Mirkin
a00727ab25 a5xx: set uint/sint bits for mrt output register
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-07 09:09:48 -04:00
Ilia Mirkin
e803023614 a5xx: add backface stencil emission
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-07 09:09:48 -04:00
Samuel Pitoiset
a584a12308 radeonsi: fix invalidating bindless buffer descriptors
The VA is stored at [4:5], not [0:1]. This invalidated all
texture buffer descriptors when they were made resident in
the current context.

This removes few partial flushes and cache invalidations which
are needed when updating a bindless descriptor on the fly with
a WRITE_DATA packet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-07 09:09:39 +02:00
Olivier Lauffenburger
43dea65ad2 st/wgl: Implement wglUseFontBitmaps.
wglUseFontBitmaps is currently a noop.
This patch implements this function for Windows.
Misc code clean-ups by Brian.

Signed-off-by: Olivier Lauffenburger <o.lauffenburger@topsolid.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-07-06 17:26:05 -06:00
Olivier Lauffenburger
80c6598cdb st/wgl: improve selection of pixel format
Current selection of pixel format does not enforce the request of
stencil or depth buffer if the color depth is not the same as
requested.

For instance, GLUT requests a 32-bit color buffer with an 8-bit
stencil buffer, but because color buffers are only 24-bit, no
priority is given to creating a stencil buffer.

This patch gives more priority to the creation of requested buffers
and less priority to the difference in bit depth.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101703
Signed-off-by: Olivier Lauffenburger <o.lauffenburger@topsolid.com>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-07-06 17:25:58 -06:00
Tim Rowley
bab03c06fc swr/rast: Correctly allocate SWR_STATS memory as cacheline aligned
Cacheline alignment of SWR_STATS to prevent sharing of cachelines
between threads (performance).

Gets rid of gcc-7.1 warning about using c++17's over-aligned new
feature.

Cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-07-06 15:01:00 -05:00
Tim Rowley
1f0680b51e swr/rast: remove unused variables
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-07-06 15:00:54 -05:00
Tim Rowley
d50ef7332c swr/rast: don't use _mm256_fmsub_ps in AVX code
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-07-06 15:00:48 -05:00
Tim Rowley
f0a22956be swr/rast: _mm*_undefined_* implementations for gcc<4.9
Define these in terms of setzero for ancient gcc versions which don't
have the undefined intrinsics.

Cc: mesa-stable@lists.freedesktop.org

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-07-06 15:00:28 -05:00
Aleksander Morgado
a6893a50c8 etnaviv: don't dereference etna_resource pointer if allocation fails
The check for the pointer being non-NULL was being done too late.

Signed-off-by: Aleksander Morgado <aleksander@aleksander.es>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-06 21:06:25 +02:00
Mauro Rossi
b7ee56b599 Android: generate symlinks for all enabled gallium drivers
Current post install command relies on GALLIUM_TARGET_DRIVERS variable,
however variable needs to be initialized in src/gallium/Android.mk
in order that all enabled gallium drivers symlinks are correctly generated.

At the moment due to sorting of INC_DIRS and variable set with svga (vmwgfx)
only vmwgfx_dri.so and virtio_gpu_dri.so symlinks are generated.

Fixes: a3d98ca62f ("Android: use symlinks for driver loading")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-05 15:10:42 +01:00
Tomeu Vizoso
79827f50e2 android: build imx-drm winsys
Add Android.mk for winsys/imx/drm.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-05 15:10:31 +01:00
Rob Herring
77c446711b android: add etnaviv driver build support
Add etnaviv to Android makefiles.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-07-05 15:10:31 +01:00
Nicolai Hähnle
c7ecbd1153 tgsi_from_mesa: add tgsi_get_gl_frag_result_semantic
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05 12:27:11 +02:00
Nicolai Hähnle
fb1c4e3d47 tgsi_from_mesa: add pipe_shader_type_from_mesa
So... the pipe_ prefix doesn't really fit into a TGSI header; on the
other hand, the return type has the pipe_ prefix.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05 12:27:11 +02:00
Nicolai Hähnle
497b95fdf6 tgsi,st/mesa: move varying slot to semantic mapping into a helper for VS
We will use this helper in radeonsi's NIR path.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-05 12:27:11 +02:00
Nicolai Hähnle
d91f97f91d ddebug: handle some cases of non-TGSI shaders
NIR shaders are not captured properly in pipelined mode currently. This
would require shader cloning, which requires linking all the Gallium
drivers against NIR. We can always do that later.

v2: avoid immediate crashes in pipelined mode

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2017-07-05 12:27:11 +02:00
Marek Olšák
a2b02c4948 gallium/radeon: fix VDPAU breakage, need VRAM with WC 2017-07-05 01:14:48 +02:00
Ilia Mirkin
1e73fc6b1a a5xx: enable polygon offset clamps
This is already set and emitted by the code.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
def1b94c33 a5xx: implement logicop support
The former 0x60 hardcoded in is equivalent to ROP_COPY with the shift.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
abe8740e33 a5xx: enable polygon mode selection
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
8108b56023 a5xx: disable ARB_depth_clamp for now
We need to figure out how to implement it properly. Right now it doesn't
work at all.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
5d9d1df183 a5xx: fix clip_halfz support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
02379b68f6 a5xx: improve 3d texture sampling
At least the first level works now. Eventually the later levels stop
working, there appears to be some alignment issue. But this improves the
situation immensely.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
c0f1efe04d a5xx: remove one of the MIPFILTER_LINEAR bits
It doesn't appear to do what we want. Removing this bit makes
lodclamp-between as well as a number of dEQP tests pass, with no visible
ill effect.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
f1fc619bd8 a5xx: enable formats newly added to the headers
This enables S3TC, BPTC, ETC2, and ASTC texture decoding. Additionally
this enables RGB32 texture buffer objects, as well as 11_11_10_FLOAT and
10_10_10_2 vertex formats (and related extensions).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
b68e22d5e2 a5xx: include color swap when decoding vertices
This fixes support for BGRA vertex formats

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin
5fdcddbeb4 a5xx: update headers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Marek Olšák
156832ee2b gallium/radeon: attempt to fix a compiler failure in radeon_winsys.h
trivial.
2017-07-04 22:40:35 +02:00
Marek Olšák
0591df025b winsys/amdgpu: use 128KB BOs for suballocations of up to 64KB BOs
This decreases the number of BOs, but might also increase memory usage.
It's better for small textures.

The gameplay is on the far right:
https://people.freedesktop.org/~mareko/suballoc.svg

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00