For emitting VK_INDIRECT_COMMANDS_TOKEN_TYPE_STATE_FLAGS_NV.
The scissor workaround for GFX9 is only needed if the state is emitted,
so move it there as well.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23584>
There's plenty of places we can use these new and shiny helpers, so
let's clean up the code a bit.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23460>
If the previous FS is NULL, some dynamic states still need to be
re-emitted.
Doesn't fix anything known.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23494>
The hardware gets given a session context from userspace in each
submission, but if the session context changes the hardware wants
a FENCE to be emitted to know it can give up the current session.
IF a test submits interleaved session ctx access and uses a single
vulkan submit the hardware crashes, unless each IB is submitted
in a separate submission so the fence can be sent.
In theory it could be possible to construct a single command buffer
to trigger this so I do think the hardware should be smarter here.
Should this be fixed in the kernel to always emit a fence between
IBs?
Fixes: dEQP-VK.video.decode.h264_interleaved
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23641>
Need to be defensive here.
Fixes recent CTS
dEQP-VK.pipeline.fast_linked_library.extended_dynamic_state.*.line_raster_mode_smooth.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23200>
iterating all the stages like this ends up unnecessarily calling
through to geometry stage binds when no shader was bound and no shader
is being bound by the power of optimization, so instead only do the unbind
part for the stages that are being unbound
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23600>
It is now set by all relevant drivers and not checked anywhere.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23191>
GFX8+ only compares the bits according to the index type by default
(GFX9 can be changed by VGT_MULTI_PRIM_IB_RESET_EN.MATCH_ALL_BITS),
so we can always leave the programmed value at the maximum.
This reduces context rolls on GFX8+ when primitive restart is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23459>
Primitive reset has a corresponding dirty state which is already
included the used_states so it is not necessary to also check
the primitive reset index here.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23459>
On RDNA2, VRS rates are part of the HTILE buffer but if we disable
HTILE completely for eg. GENERAL, VRS rates aren't read by the hw.
Fix this by disabling HTILE compression which should have the same
effect without VRS.
Fixes recent
dEQP-VK.fragment_shading_rate.renderpass2.monolithic.attachment_rate.misc.*
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
DB_RENDER_CONTROL controls whether depth/stencil rendering should be
compressed. Emitting this register as part of the framebuffer will
allow us to keep HTILE enabled for VRS rates, instead of disabling it
completely.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23209>
It's unclear why this is needed, but PAL uses RESET_FILTER_CAM
for some mesh shading draw packets:
- DISPATCH_MESH_INDIRECT_MULTI
- DISPATCH_TASKMESH_GFX
Let's do the same in radv.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23554>
Equivalent of 284e604872 but for acceleration structure queries.
If an app inserts a barrier between AS builds and writing AS properties,
we must respect it or things will blow up.
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23568>
radeonsi switched over to CU wavefront execution mode, but didn't tell
LLVM. This can lead to shaders requiring too many VGPRs to be executed in
CU mode and so cause GPU resets.
Pass along +cumode to LLVM so it properly spills VGPRs.
Fixes: 9d7eab2ab1 ("radeonsi: don't enable WGP_MODE because of high cost of workgroup mem coherency")
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23569>
PIPE_FUNC_ -> COMPARE_FUNC_
pipe_compare_func -> compare_func
Now include "pipe/p_state.h" is not needed and remove it in ac_nir.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23422>
amdgpu enables gfxoff by default and the feature resets the RLC clock
counter on idle on raven/raven2. Querying AMDGPU_INFO_TIMESTAMP does
not work as expected on those platforms.
There was an attempt in amdgpu to read from the TSC register instead,
but it did not work without a firmware update[1]. Another possible
solution is to disable the clock counter reset by clearing
AMD_PG_SUPPORT_RLC_SMU_HS, but that causes a 0.2W increase of power
consumption on idle which is undesirable.
The clock counter reset affects vkCmdWriteTimestamp as well. The spec
is vague on whether that is allowed or not. The WG is aware of the
issue[2] but never really addresses it.
[1] https://lists.freedesktop.org/archives/amd-gfx/2023-May/093731.html
[2] https://github.com/KhronosGroup/Vulkan-Docs/issues/216
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23481>
This reduce LDS bank conflict and align with radeonsi,
so we don't assume LDS access 16 byte aligned for both
driver.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23314>
