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nir: use nir_imm_{true,false}

Browse source 
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23461>
This commit is contained in:
Erik Faye-Lund 2023-06-05 14:54:54 +02:00 • committed by Marge Bot
parent 9e5cd02fae
commit 590e191e77
14 changed files with 30 additions and 30 deletions
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2
src/amd/common/ac_nir.c
View file

@ -777,7 +777,7 @@ ac_nir_gs_shader_query(nir_builder *b,
nir_if *if_shader_query = nir_push_if(b, shader_query_enabled);
nir_ssa_def *active_threads_mask = nir_ballot(b, 1, wave_size, nir_imm_bool(b, true));
nir_ssa_def *active_threads_mask = nir_ballot(b, 1, wave_size, nir_imm_true(b));
nir_ssa_def *num_active_threads = nir_bit_count(b, active_threads_mask);
/* Calculate the "real" number of emitted primitives from the emitted GS vertices and primitives.

6
src/amd/common/ac_nir_cull.c
View file

@ -21,9 +21,9 @@ static void
analyze_position_w(nir_builder *b, nir_ssa_def *pos[][4], unsigned num_vertices,
position_w_info *w_info)
{
w_info->all_w_negative = nir_imm_bool(b, true);
w_info->w_reflection = nir_imm_bool(b, false);
w_info->any_w_negative = nir_imm_bool(b, false);
w_info->all_w_negative = nir_imm_true(b);
w_info->w_reflection = nir_imm_false(b);
w_info->any_w_negative = nir_imm_false(b);
for (unsigned i = 0; i < num_vertices; ++i) {
nir_ssa_def *neg_w = nir_flt_imm(b, pos[i][3], 0.0f);

10
src/amd/common/ac_nir_lower_ngg.c
View file

@ -1520,7 +1520,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
nir_scoped_barrier(b, .execution_scope=NIR_SCOPE_WORKGROUP, .memory_scope=NIR_SCOPE_WORKGROUP,
.memory_semantics=NIR_MEMORY_ACQ_REL, .memory_modes=nir_var_mem_shared);
nir_store_var(b, s->gs_accepted_var, nir_imm_bool(b, false), 0x1u);
nir_store_var(b, s->gs_accepted_var, nir_imm_false(b), 0x1u);
nir_store_var(b, s->prim_exp_arg_var, nir_imm_int(b, 1u << 31), 0x1u);
/* GS invocations load the vertex data and perform the culling. */
@ -1560,7 +1560,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
/* primitive is culled if any plane's clipdist of all vertices are negative */
accepted_by_clipdist = nir_ieq_imm(b, clipdist_neg_mask, 0);
} else {
accepted_by_clipdist = nir_imm_bool(b, true);
accepted_by_clipdist = nir_imm_true(b);
}
/* See if the current primitive is accepted */
@ -1573,7 +1573,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
nir_scoped_barrier(b, .execution_scope=NIR_SCOPE_WORKGROUP, .memory_scope=NIR_SCOPE_WORKGROUP,
.memory_semantics=NIR_MEMORY_ACQ_REL, .memory_modes=nir_var_mem_shared);
nir_store_var(b, s->es_accepted_var, nir_imm_bool(b, false), 0x1u);
nir_store_var(b, s->es_accepted_var, nir_imm_false(b), 0x1u);
/* ES invocations load their accepted flag from LDS. */
if_es_thread = nir_push_if(b, es_thread);
@ -1849,7 +1849,7 @@ ngg_build_streamout_buffer_info(nir_builder *b,
nir_ssa_def *emit_prim[4];
memcpy(emit_prim, gen_prim, 4 * sizeof(nir_ssa_def *));
nir_ssa_def *any_overflow = nir_imm_bool(b, false);
nir_ssa_def *any_overflow = nir_imm_false(b);
nir_ssa_def *overflow_amount[4] = {undef, undef, undef, undef};
for (unsigned buffer = 0; buffer < 4; buffer++) {
@ -3144,7 +3144,7 @@ ngg_gs_cull_primitive(nir_builder *b, nir_ssa_def *tid_in_tg, nir_ssa_def *max_v
}
/* TODO: support clipdist culling in GS */
nir_ssa_def *accepted_by_clipdist = nir_imm_bool(b, true);
nir_ssa_def *accepted_by_clipdist = nir_imm_true(b);
nir_ssa_def *accepted = ac_nir_cull_primitive(
b, accepted_by_clipdist, pos, s->num_vertices_per_primitive, NULL, NULL);

8
src/amd/vulkan/meta/radv_meta_etc_decode.c
View file

@ -256,7 +256,7 @@ build_shader(struct radv_device *dev)
nir_variable *etc1_compat =
nir_variable_create(b.shader, nir_var_shader_temp, glsl_bool_type(), "etc1_compat");
nir_store_var(&b, etc1_compat, nir_imm_bool(&b, false), 0x1);
nir_store_var(&b, etc1_compat, nir_imm_false(&b), 0x1);
nir_variable *alpha_result =
nir_variable_create(b.shader, nir_var_shader_temp, glsl_float_type(), "alpha_result");
@ -286,7 +286,7 @@ build_shader(struct radv_device *dev)
nir_push_if(
&b, nir_iand(&b, nir_inot(&b, alpha_bits_1), nir_inot(&b, nir_test_mask(&b, color_y, 2))));
{
nir_store_var(&b, etc1_compat, nir_imm_bool(&b, true), 1);
nir_store_var(&b, etc1_compat, nir_imm_true(&b), 1);
nir_ssa_def *tmp[3];
for (unsigned i = 0; i < 3; ++i)
tmp[i] = etc_extend(
@ -407,11 +407,11 @@ build_shader(struct radv_device *dev)
nir_channel(&b, pixel_coord, 1));
rgb = nir_iadd(&b, rgb, nir_ishr_imm(&b, nir_iadd_imm(&b, nir_iadd(&b, dx, dy), 2), 2));
nir_store_var(&b, rgb_result, rgb, 0x7);
nir_store_var(&b, punchthrough, nir_imm_bool(&b, false), 0x1);
nir_store_var(&b, punchthrough, nir_imm_false(&b), 0x1);
}
nir_push_else(&b, NULL);
{
nir_store_var(&b, etc1_compat, nir_imm_bool(&b, true), 1);
nir_store_var(&b, etc1_compat, nir_imm_true(&b), 1);
nir_ssa_def *subblock_b = nir_ine_imm(&b, subblock, 0);
nir_ssa_def *tmp[] = {
nir_bcsel(&b, subblock_b, r1, rb),

4
src/amd/vulkan/nir/radv_nir_lower_ray_queries.c
View file

@ -336,7 +336,7 @@ insert_terminate_on_first_hit(nir_builder *b, nir_ssa_def *index, struct ray_que
SpvRayFlagsTerminateOnFirstHitKHRMask);
nir_push_if(b, terminate_on_first_hit);
{
rq_store_var(b, index, vars->incomplete, nir_imm_bool(b, false), 0x1);
rq_store_var(b, index, vars->incomplete, nir_imm_false(b), 0x1);
if (break_on_terminate)
nir_jump(b, nir_jump_break);
}
@ -672,7 +672,7 @@ static void
lower_rq_terminate(nir_builder *b, nir_ssa_def *index, nir_intrinsic_instr *instr,
struct ray_query_vars *vars)
{
rq_store_var(b, index, vars->incomplete, nir_imm_bool(b, false), 0x1);
rq_store_var(b, index, vars->incomplete, nir_imm_false(b), 0x1);
}
bool

2
src/amd/vulkan/radv_device_generated_commands.c
View file

@ -480,7 +480,7 @@ build_dgc_prepare_shader(struct radv_device *dev)
nir_ssa_def *convert_cond =
nir_ine_imm(&b, nir_load_var(&b, num_records), 0);
if (dev->physical_device->rad_info.gfx_level == GFX9)
convert_cond = nir_imm_bool(&b, false);
convert_cond = nir_imm_false(&b);
else if (dev->physical_device->rad_info.gfx_level != GFX8)
convert_cond =
nir_iand(&b, convert_cond, nir_ieq_imm(&b, stride, 0));

8
src/amd/vulkan/radv_rt_common.c
View file

@ -402,8 +402,8 @@ hit_is_opaque(nir_builder *b, nir_ssa_def *sbt_offset_and_flags,
nir_ssa_def *opaque =
nir_uge_imm(b, nir_ior(b, geometry_id_and_flags, sbt_offset_and_flags),
RADV_INSTANCE_FORCE_OPAQUE | RADV_INSTANCE_NO_FORCE_NOT_OPAQUE);
opaque = nir_bcsel(b, ray_flags->force_opaque, nir_imm_bool(b, true), opaque);
opaque = nir_bcsel(b, ray_flags->force_not_opaque, nir_imm_bool(b, false), opaque);
opaque = nir_bcsel(b, ray_flags->force_opaque, nir_imm_true(b), opaque);
opaque = nir_bcsel(b, ray_flags->force_not_opaque, nir_imm_false(b), opaque);
return opaque;
}
@ -555,7 +555,7 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_push_if(b, nir_ilt_imm(b, nir_load_deref(b, args->vars.stack),
args->stack_base + args->stack_stride));
{
nir_store_var(b, incomplete, nir_imm_bool(b, false), 0x1);
nir_store_var(b, incomplete, nir_imm_false(b), 0x1);
nir_jump(b, nir_jump_break);
}
nir_pop_if(b, NULL);
@ -592,7 +592,7 @@ radv_build_ray_traversal(struct radv_device *device, nir_builder *b,
nir_ssa_def *parent = fetch_parent_node(b, bvh_addr, prev);
nir_push_if(b, nir_ieq_imm(b, parent, RADV_BVH_INVALID_NODE));
{
nir_store_var(b, incomplete, nir_imm_bool(b, false), 0x1);
nir_store_var(b, incomplete, nir_imm_false(b), 0x1);
nir_jump(b, nir_jump_break);
}
nir_pop_if(b, NULL);

2
src/compiler/nir/nir_inline_functions.c
View file

@ -112,7 +112,7 @@ void nir_inline_function_impl(struct nir_builder *b,
nir_cf_list_extract(&body, &copy->body);
if (nest_if) {
nir_if *cf = nir_push_if(b, nir_imm_bool(b, true));
nir_if *cf = nir_push_if(b, nir_imm_true(b));
nir_cf_reinsert(&body, nir_after_cf_list(&cf->then_list));
nir_pop_if(b, cf);
} else {

2
src/compiler/nir/nir_lower_is_helper_invocation.c
View file

@ -51,7 +51,7 @@ nir_lower_load_and_store_is_helper(nir_builder *b, nir_instr *instr, void *data)
switch (intrin->intrinsic) {
case nir_intrinsic_demote: {
b->cursor = nir_before_instr(instr);
nir_store_deref(b, is_helper_deref, nir_imm_bool(b, true), 1);
nir_store_deref(b, is_helper_deref, nir_imm_true(b), 1);
return true;
}
case nir_intrinsic_demote_if: {

2
src/compiler/nir/nir_lower_tex.c
View file

@ -1309,7 +1309,7 @@ nir_lower_lod_zero_width(nir_builder *b, nir_tex_instr *tex)
b->cursor = nir_after_instr(&tex->instr);
nir_ssa_def *is_zero = nir_imm_bool(b, true);
nir_ssa_def *is_zero = nir_imm_true(b);
for (unsigned i = 0; i < tex->coord_components; i++) {
nir_ssa_def *coord = nir_channel(b, tex->src[coord_index].src.ssa, i);

2
src/gallium/drivers/radeonsi/si_nir_lower_abi.c
View file

@ -424,7 +424,7 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
break;
case nir_intrinsic_load_cull_ccw_amd:
/* radeonsi embed cw/ccw info into front/back face enabled */
replacement = nir_imm_bool(b, false);
replacement = nir_imm_false(b);
break;
case nir_intrinsic_load_cull_any_enabled_amd:
replacement = nir_imm_bool(b, !!key->ge.opt.ngg_culling);

8
src/mesa/state_tracker/st_pbo_compute.c
View file

@ -297,9 +297,9 @@ init_pbo_shader_data(nir_builder *b, struct pbo_shader_data *sd, unsigned coord_
nir_ball(b, nir_ieq_imm(b, sd->bits, 8)),
nir_ball(b, nir_ieq_imm(b, nir_channels(b, sd->bits, 7), 8))),
nir_ball(b, nir_ieq_imm(b, nir_channels(b, sd->bits, 3), 8))),
nir_imm_bool(b, 0)),
nir_imm_bool(b, 0))),
nir_imm_bool(b, 0),
nir_imm_false(b)),
nir_imm_false(b))),
nir_imm_false(b),
sd->swap);
*/
}
@ -494,7 +494,7 @@ check_for_weird_packing(nir_builder *b, struct pbo_shader_data *sd, unsigned com
nir_ior(b,
nir_ine(b, c, sd->bits1),
nir_ine_imm(b, nir_imod(b, c, nir_imm_int(b, 8)), 0)),
nir_imm_bool(b, 0));
nir_imm_false(b));
}
/* convenience function for clamping signed integers */

2
src/microsoft/compiler/dxil_nir.c
View file

@ -2196,7 +2196,7 @@ lower_subgroup_scan(nir_builder *b, nir_instr *instr, void *data)
b->cursor = nir_before_instr(instr);
nir_op op = nir_intrinsic_reduction_op(intr);
nir_ssa_def *subgroup_id = nir_build_load_subgroup_invocation(b);
nir_ssa_def *active_threads = nir_build_ballot(b, 4, 32, nir_imm_bool(b, true));
nir_ssa_def *active_threads = nir_build_ballot(b, 4, 32, nir_imm_true(b));
nir_ssa_def *base_value;
uint32_t bit_size = intr->dest.ssa.bit_size;
if (op == nir_op_iand || op == nir_op_umin)

2
src/microsoft/vulkan/dzn_nir.c
View file

@ -925,7 +925,7 @@ dzn_nir_polygon_point_mode_gs(const nir_shader *previous_shader, struct dzn_nir_
nir_deref_instr *loop_index_deref = nir_build_deref_var(b, loop_index_var);
nir_store_deref(b, loop_index_deref, nir_imm_int(b, 0), 1);
nir_ssa_def *cull_pass = nir_imm_bool(b, true);
nir_ssa_def *cull_pass = nir_imm_true(b);
nir_ssa_def *front_facing;
assert(info->cull_mode != VK_CULL_MODE_FRONT_AND_BACK);
if (info->cull_mode == VK_CULL_MODE_FRONT_BIT) {