Commit graph

161161 commits

Author SHA1 Message Date
Yonggang Luo
44ccaca41d util/mesa/wide: Rename _SIMPLE_MTX_INITIALIZER_NP to SIMPLE_MTX_INITIALIZER
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18393>
2022-10-14 03:27:41 +00:00
Guilherme Gallo
be3c46964b ci/bin: Remove whitespace from token files
There was a security problem with some `gitlab_gql.py` scenarios because
of `\r` and `\n` in the token file, which interrupted the requests for
Gitlab endpoints.

Stripping the token file after reading the file content solves the
problem.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>
2022-10-14 01:46:52 +00:00
Guilherme Gallo
d52d51b24d ci/bin: Fix requirements.txt
Add missing aiohttp and PyYAML packages

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18066>
2022-10-14 01:46:52 +00:00
Alyssa Rosenzweig
bb6c43027e agx: Reserve live-in regs at the start of block
...Rather than reserving the union of the registers live-out of the
predecessors. This avoids reserving registers that are killed along a
control flow edge (where the predecessor has another successor that does
use the register).

glmark2 subset of shaderdb:

total instructions in shared programs: 6442 -> 6440 (-0.03%)
instructions in affected programs: 42 -> 40 (-4.76%)
helped: 1
HURT: 0

total bytes in shared programs: 42186 -> 42174 (-0.03%)
bytes in affected programs: 270 -> 258 (-4.44%)
helped: 1
HURT: 0

total halfregs in shared programs: 1769 -> 1757 (-0.68%)
halfregs in affected programs: 75 -> 63 (-16.00%)
helped: 3
HURT: 0
helped stats (abs) min: 4.0 max: 4.0 x̄: 4.00 x̃: 4
helped stats (rel) min: 16.00% max: 16.00% x̄: 16.00% x̃: 16.00%

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
de6e11b848 agx: Pass in max regs as a paramter to RA
This will allow us to restrict max regs later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
68f89d4cc5 agx: Introduce ra_ctx data structure
We have more parameters to pass, this will get unwieldly otherwise.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
bcb2cf9688 agx: Write to r0l with a "nesting" instruction
This avoids modeling the r0l register explicitly in the IR, which would
complicate RA for little benefit at this stage. Do the simplest thing
that could possibly work in SSA.

glmark2 subset.

total instructions in shared programs: 6442 -> 6442 (0.00%)
instructions in affected programs: 701 -> 701 (0.00%)
helped: 4
HURT: 5
helped stats (abs) min: 1.0 max: 3.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 1.46% max: 7.69% x̄: 4.03% x̃: 3.48%
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.60 x̃: 1
HURT stats (rel)   min: 0.81% max: 7.41% x̄: 2.67% x̃: 1.14%
95% mean confidence interval for instructions value: -1.58 1.58
95% mean confidence interval for instructions %-change: -3.70% 3.08%
Inconclusive result (value mean confidence interval includes 0).

total bytes in shared programs: 42196 -> 42186 (-0.02%)
bytes in affected programs: 7768 -> 7758 (-0.13%)
helped: 8
HURT: 5
helped stats (abs) min: 2.0 max: 18.0 x̄: 7.25 x̃: 4
helped stats (rel) min: 0.13% max: 7.26% x̄: 2.02% x̃: 0.97%
HURT stats (abs)   min: 6.0 max: 18.0 x̄: 9.60 x̃: 6
HURT stats (rel)   min: 0.82% max: 6.32% x̄: 2.37% x̃: 1.02%
95% mean confidence interval for bytes value: -7.02 5.48
95% mean confidence interval for bytes %-change: -2.30% 1.63%
Inconclusive result (value mean confidence interval includes 0).

total halfregs in shared programs: 1926 -> 1769 (-8.15%)
halfregs in affected programs: 1395 -> 1238 (-11.25%)
helped: 71
HURT: 0
helped stats (abs) min: 1.0 max: 10.0 x̄: 2.21 x̃: 2
helped stats (rel) min: 1.92% max: 52.63% x̄: 15.33% x̃: 11.76%
95% mean confidence interval for halfregs value: -2.69 -1.73
95% mean confidence interval for halfregs %-change: -17.98% -12.68%
Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
c9a96d4615 agx: Preload vertex/instance ID only at start
This means we don't reserve the registers, which improves RA
considerably. Using a special preload psuedo-op instead of a regular
move allows us to constrain semantics and gaurantee coalescing.

shader-db on glmark2 subset:

total instructions in shared programs: 6448 -> 6442 (-0.09%)
instructions in affected programs: 230 -> 224 (-2.61%)
helped: 4
HURT: 0

total bytes in shared programs: 42232 -> 42196 (-0.09%)
bytes in affected programs: 1530 -> 1494 (-2.35%)
helped: 4
HURT: 0

total halfregs in shared programs: 2291 -> 1926 (-15.93%)
halfregs in affected programs: 2185 -> 1820 (-16.70%)
helped: 75
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
f665229d77 agx: Print agx_dim appropriately
Easier to read, and gets us closer to proper disasm in Mesa.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
6c95572ef0 agx: Print instructions as "dest = src"
This makes the dataflow easier to read, especially with splits and
collects (which take variable numbers of sources/destinations).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
72a1e1f33f agx: Emit trap at pack-time, not during isel
This makes the shaderdb stats make more sense.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
1dcaade3e2 agx: Rename "combine" to "collect"
For consistency with ir3 and bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
82e8e709cb agx: Dynamically size split instruction
This is more flexible.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
7c9fba34bc agx: Switch to dynamic allocation of srcs/dests
So we can handle parallel copies later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
544c60a132 agx: Improve printing of immediate sources
For floats, decode the float. Regardless, the size speciifer is
redundant.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
c2bc8c1384 agx: Don't prefix pseudo-ops
It's not really buying us anything and it clutters the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
40f0ac2082 agx: Emit smaller combines for nir_op_vec2/3
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
f4726cf240 agx: Set PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
Avoids spilling in t-rex.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Alyssa Rosenzweig
6a183a9ffd agx: Add iterators for phi/non-phi instructions
We know that phi nodes are always at the start (this is asserted in
agx_validate and a fundamental invariant of SSA form). That means we can
cheaply iterate all n phi nodes forward (or n non-phi nodes backwards)
in O(n) time. We already open code this idiom in a few places, use
common iterators instead so we don't need to justify in random places.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
2022-10-14 01:37:39 +00:00
Mike Blumenkrantz
d3880a6324 zink: disable fbfetch when flushing clears
this ensures there's no weird perf happening, avoids using renderpass
instead of dynamic rendering, and avoids hitting an assert from broken
framebuffer construction

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
1ae26de36f zink: unset rp_changed after initializing renderpass attachments
if fbfetch is setup here, it will flag rp_changed

this is already inside renderpass setup, however, so just unset it
to avoid erroneously trigering the assert

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
f72071fbc3 zink: clamp line_stipple_factor to 1 if stipple is disabled
0 is technically an illegal value even though it won't be read in this case

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
2710ef4c2a zink: don't add other usage bits for transient images
this is illegal

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
2022-10-14 01:16:30 +00:00
Mike Blumenkrantz
3dcc03d979 zink: check core feature for pipeline cache control
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19065>
2022-10-14 01:16:30 +00:00
Emma Anholt
179e638bb8 zink: Fix dummy CB path decision for VK_EXT_cwe presence.
We have to do the dummy workaround when we *don't* have the ext.  This was
apparently a mis-sedding.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19057>
2022-10-14 00:55:36 +00:00
Karol Herbst
6a18e154bc rusticl/mem: propper CL_MEM_ALLOC_HOST_PTR support
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Karol Herbst
7195b62c63 lp: claim being UMA
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Karol Herbst
72f763f5cc rusticl/mem: rewrite the (un)mapping code
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Karol Herbst
dc081353ac rusticl: add helper ctx wrapper for coherent and direct mapping
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Karol Herbst
ea5b23c75b rusticl: rework resource mappings a little
The _async variants will be removed later.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Karol Herbst
6b235361f7 rusticl/mesa: add bx() method to PipeTransfer
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Karol Herbst
557f4dd89a rusticl: add support for coherent resources
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18793>
2022-10-13 23:15:33 +00:00
Timothy Arceri
a5e9e64aae glthread: fix matrix stack depth tracking
Dont bump the depth if the application attempts to overflow or
underflow the stack.

Fixes: 6febe2b880 ("glthread: track all matrix stack depths")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19059>
2022-10-13 22:47:49 +00:00
Alyssa Rosenzweig
6689d67603 asahi: Remove no-direct-packing
It's weird.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:52 -04:00
Alyssa Rosenzweig
ea58edaafb asahi: Use a header more like Intel's GenXML
We're trying to converge on a common schema.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:52 -04:00
Alyssa Rosenzweig
ab2d5deec2 asahi,panfrost: Remove exact attribute
Not used, although in the future it might be...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:52 -04:00
Alyssa Rosenzweig
a64e38b0aa panfrost,asahi: Remove unused function
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:51 -04:00
Alyssa Rosenzweig
0f24c8ef5f panfrost,asahi: Remove unused prepare macro
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:51 -04:00
Alyssa Rosenzweig
0302519f1c asahi/genxml: Defeature uint/float
Unused, relic from panfrost and not in upstream genxml.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:51 -04:00
Alyssa Rosenzweig
8eefda4ea9 asahi: Eliminate "Pixel Format" type from GenXML
This is leaky and hurts compatibility with upstream GenXML. Just use the
actual hardware fields.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-10-13 18:06:51 -04:00
Alyssa Rosenzweig
f4b03ea6dc nir/lower_system_values: Fix cs_local_index_to_id with variable workgroups
In that case we need to use the sysval. That sysval can be optimized anyway in
the nonvariable case. Fixes test_basic.get_linear_ids on panfrost.

Fixes: 998d84fca5 ("nir/lower_system_values: Support lowering more intrinsics")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18662>
2022-10-13 21:25:23 +00:00
Kenneth Graunke
2dfab687ec intel/compiler: Vectorize gl_TessLevelInner/Outer[] writes [v2]
Setting the NIR options takes care of iris thanks to the common st/mesa
linking code, and updating brw_nir_link_shaders should handle anv.

The main effort here is updating remap_tess_levels, which needs to
handle vector stores, writemasking, and swizzling.  Unfortunately,
we also need to continue handling the existing single-component
access because it's used for TES inputs, which we don't vectorize.

We could try to vectorize TES inputs too, but they're all pushed
anyway, so it wouldn't buy us much other than deleting this code.
Also, we do have opt_combine_stores, but not one for loads.

One limitation of using nir_vectorize_tess_levels is that it works
on variables, and so isn't able to combine outer/inner writes that
happen to live in the same vec4 slot (for triangle domains).  That
said, it's still better than before.

For writes, we allow the intrinsics to supply up to the full size
of the variable (vec4 for outer, vec2 for inner) even if the domain
only requires a subset of those components (i.e. triangles needs 3).

shader-db results on Icelake:

   total instructions in shared programs: 19600314 -> 19597528 (-0.01%)
   instructions in affected programs: 65338 -> 62552 (-4.26%)
   helped: 271 / HURT: 0
   helped stats (abs) min: 6 max: 24 x̄: 10.28 x̃: 12
   helped stats (rel) min: 1.30% max: 18.18% x̄: 5.80% x̃: 7.59%
   95% mean confidence interval for instructions value: -10.71 -9.85
   95% mean confidence interval for instructions %-change: -6.17% -5.43%
   Instructions are helped.

   total cycles in shared programs: 851842332 -> 851808165 (<.01%)
   cycles in affected programs: 618577 -> 584410 (-5.52%)
   helped: 271 / HURT: 0
   helped stats (abs) min: 64 max: 540 x̄: 126.08 x̃: 111
   helped stats (rel) min: 2.57% max: 37.97% x̄: 6.12% x̃: 5.06%
   95% mean confidence interval for cycles value: -135.35 -116.80
   95% mean confidence interval for cycles %-change: -6.67% -5.57%
   Cycles are helped.

   total sends in shared programs: 1025238 -> 1024308 (-0.09%)
   sends in affected programs: 6454 -> 5524 (-14.41%)
   helped: 271 / HURT: 0
   helped stats (abs) min: 2 max: 8 x̄: 3.43 x̃: 4
   helped stats (rel) min: 5.71% max: 25.00% x̄: 14.98% x̃: 17.39%
   95% mean confidence interval for sends value: -3.57 -3.29
   95% mean confidence interval for sends %-change: -15.42% -14.54%
   Sends are helped.

According to Felix DeGrood, this results in a 10% improvement in
the draw call time for certain draw calls from Strange Brigade.

v2: Fix assertions about number of components and add more of them.
    Combine the quads and triangles handling as it's nearly identical.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19061>
2022-10-13 11:38:21 -07:00
semjon00
44d917bdf3 hasvk: force inline more pipe flush functions
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
2022-10-13 14:21:38 +00:00
semjon00
760b43f32c hasvk: combine flushes in Draw/DrawIndexed/DrawIndirectByteCountEXT
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
2022-10-13 14:21:38 +00:00
semjon00
bee1f7b83a hasvk: don't export gfx state flushing helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
2022-10-13 14:21:38 +00:00
semjon00
6db3a82fb2 hasvk: don't export flush_compute_state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18965>
2022-10-13 14:21:38 +00:00
Yonggang Luo
4f0f272069 util: Implement atomic operations consistently across compilers and testing for it
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18795>
2022-10-13 13:51:18 +00:00
Yonggang Luo
96e7d1cf0c util: Remove the include of windows.h when compiling with MSVC
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7345

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18795>
2022-10-13 13:51:18 +00:00
Karol Herbst
1c86a5f309 rusticl/kernel: preserve fp16 denorms to fix vload/vstore_half
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19041>
2022-10-13 13:13:54 +00:00
Yiwei Zhang
5fa7c53631 venus: avoid accessing local var in VN_ADD_EXT_TO_PNEXT_OF
This boring refactor:
- makes it consistent for extension name alias
- shortens the line a bit to not further regress line width
- applies macro when possible to be consistent
- removes some redundant empty lines

v2: rebase

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chadversary@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18993>
2022-10-13 05:35:26 +00:00