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Author SHA1 Message Date
Thomas H.P. Andersen
436e59e3d9 tgsi: remove unused tgsi_shader_info fields 
Removes:
uses_persp_opcode_interp_centroid
uses_persp_opcode_interp_offset
uses_persp_opcode_interp_sample
uses_linear_opcode_interp_centroid
uses_linear_opcode_interp_offset
uses_linear_opcode_interp_sample

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
6c513ef4fd tgsi: remove unused tgsi_shader_info fields 
Removes:
uses_persp_center
uses_persp_centroid
uses_persp_sample
uses_linear_center
uses_linear_centroid
uses_linear_sample

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
76b0e7b25c tgsi: remove unused tgsi_shader_info.reads_tess_factors 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
9050b10627 svga: remove unused struct field 
This will allow further cleanup in tgsi_shader_info

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
29673ac8d0 tgsi: remove unused tgsi_shader_info.reads_samplemask 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
ad2c811884 tgsi: remove unused tgsi_shader_info.reads_position 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
1f1ffd5b1d tgsi: remove unused tgsi_shader_info.colors_written 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
9684fbc87d tgsi: remove unused tgsi_shader_info.colors_read 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
849065b9f3 tgsi: remove unused tgsi_shader_info.num_memory_instructions 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
64ce4669a3 tgsi: remove unused tgsi_shader_info.array_max 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:27 +00:00
Thomas H.P. Andersen
8807f0ec3e tgsi: remove unused tgsi_shader_info.num_tokens 
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24100>
 2023-07-19 12:41:26 +00:00
Dr. David Alan Gilbert
69101c72f3 rusticl: Wire the 'start' and 'end' profilng times up 
We use the timestamp pipe queries to retrieve times from the
device, hopefully close to the execution of the code.

For now we use the End value for complete as well.

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24101>
 2023-07-19 10:29:25 +00:00
Dr. David Alan Gilbert
4a44dd1654 rusticl: Wrap pipe query reads 
Take a query we previously created and read it's result.
The type of the result is usually implicitly known; for now
just handle the query we use in 64 bit.

This is safe because the trait bindings ensure that
when we create a query with PipeQueryGen we embed the type
of the result in the PipeQuery, and that produces the correct
result type.

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24101>
 2023-07-19 10:29:25 +00:00
Dr. David Alan Gilbert
52e53938c3 rusticl: Wrap pipe queries 
Pipe queries are asynchronous state reads, you create a query
and sometime later retrieve the result.

Wrap the underlying basic calls and types and provide a type
(PipeQuery) to handle the lifetype of the query.  Note the pipe context
used for the query must live at last as long as the query.

Queries are created by calls to the PipeQueryGen, a wrapper
that figures out the return type and wraps that in the intermediate
that's returned.   A typical use is:

  query_start = PipeQueryGen::<{pipe_query_type::PIPE_QUERY_TIMESTAMP}>::new(ctx);

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24101>
 2023-07-19 10:29:25 +00:00
Dr. David Alan Gilbert
c893fa1fcd rusticl: Wire the 'submit' profiling time up 
Set it from the timestamp when it's taken out of the queue and
submitted, and wire the APU up to read it.

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24101>
 2023-07-19 10:29:25 +00:00
Dr. David Alan Gilbert
85ca349be0 rusticl: Wire the 'queued' profiling time up 
Set it from the timestamp when it's added to the queue, and wire
the API up to read it.

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24101>
 2023-07-19 10:29:24 +00:00
Dr. David Alan Gilbert
6052e58bf6 rusticl/core: Add profiling time storage (queued) to event 
Add the first, of a few, profiling time values to the Event,
with access methods.  This is defined as

   'when the command identified by event is enqueued in a command-queue
    by the host'

Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24101>
 2023-07-19 10:29:24 +00:00
Karol Herbst
a944a8eba9 nvc0: initial Ada enablement 
Cc: 23.2 <mesa-stable>
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24226>
 2023-07-19 09:08:16 +00:00
Philipp Zabel
f626605cbf etnaviv: fix segfault after compile failure 
Do not try to determine the shader stage from the compiled shader
variant, which may be NULL after compile failure. Instead, get it
from the NIR shader.

Fixes a segfault when trying to evaluate etna_shader_stage(NULL)
after compile failure.

Suggested-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Fixes: 3d49619071 ("etnaviv: add support for performance warnings")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24178>
 2023-07-19 08:46:22 +00:00
Honglei Huang
b246f96573 virgl: Enable vp9 hardware decode 
Add vp9 fill function in fill_picture_desc to enable vp9 decoding.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:38 +00:00
Boyuan Zhang
d4220c14cc virgl: Implement vp9 hardware decode 
Implement vp9 hardware decode by filling vp9 picture desc.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:38 +00:00
Honglei Huang
15a2b1797b virgl/video: Add jpeg buf start code check 
Add jpeg start code check to fix the issue that
double header adding in virgl video codec.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:38 +00:00
Honglei Huang
9cbb7cb13b virgl/video: Add more pipe type in virgl formats convert table 
Add Y8_400_UNORM, YUYV, Y8_U8_V8_444_UNORM,
R8G8_R8B8_UNORM into virgl_formats_conv_table to fix
the resource create fail issue.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:38 +00:00
Honglei Huang
2b6301e870 virgl/video: Add support for hevc10bit decoding. 
Add P010 CONV_FORMAT to support virgl hevc10bit decoding.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:38 +00:00
Honglei Huang
e1b8e4d7fc virgl/video: Add support for jpeg decoding 
Implement for virgl jpeg decoding.

Signed-off-by: Honglei Huang <honghuan@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:38 +00:00
Honglei Huang
dad4b79ee0 virgl/video: Add support for vc1 decoding 
Implement for virgl vc1 decoding.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:37 +00:00
Honglei Huang
deafeab1ee virgl/video: Add support for mpeg12 decoding 
Implement for mpeg12 virgl video decoding.

Signed-off-by: Honglei Huang <honglei1.huang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22108>
 2023-07-19 07:06:37 +00:00
Faith Ekstrand
ce75c3c3fe intel: Switch to intrinsic-based registers 
Results on HSW (vec4 only):

    total instructions in shared programs: 2978400 -> 2974135 (-0.14%)
    instructions in affected programs: 77870 -> 73605 (-5.48%)
    helped: 143
    HURT: 48
    helped stats (abs) min: 1 max: 100 x̄: 30.22 x̃: 9
    helped stats (rel) min: 0.03% max: 30.49% x̄: 8.02% x̃: 6.39%
    HURT stats (abs)   min: 1 max: 4 x̄: 1.19 x̃: 1
    HURT stats (rel)   min: 0.08% max: 16.67% x̄: 3.71% x̃: 3.23%
    95% mean confidence interval for instructions value: -26.69 -17.97
    95% mean confidence interval for instructions %-change: -6.24% -3.90%
    Instructions are helped.

    total cycles in shared programs: 45345924 -> 44742666 (-1.33%)
    cycles in affected programs: 29083466 -> 28480208 (-2.07%)
    helped: 4785
    HURT: 3879
    helped stats (abs) min: 2 max: 8072 x̄: 276.00 x̃: 24
    helped stats (rel) min: 0.02% max: 54.43% x̄: 7.78% x̃: 1.95%
    HURT stats (abs)   min: 2 max: 14736 x̄: 184.95 x̃: 20
    HURT stats (rel)   min: 0.02% max: 97.00% x̄: 7.69% x̃: 1.53%
    95% mean confidence interval for cycles value: -83.49 -55.77
    95% mean confidence interval for cycles %-change: -1.16% -0.55%
    Cycles are helped.

    total spills in shared programs: 1093 -> 539 (-50.69%)
    spills in affected programs: 772 -> 218 (-71.76%)
    helped: 74
    HURT: 0

    total fills in shared programs: 760 -> 757 (-0.39%)
    fills in affected programs: 66 -> 63 (-4.55%)
    helped: 3
    HURT: 0

Results on TGL (all stages):

    total instructions in shared programs: 21486982 -> 21488266 (<.01%)
    instructions in affected programs: 2245938 -> 2247222 (0.06%)
    helped: 1288
    HURT: 1385
    helped stats (abs) min: 1 max: 93 x̄: 4.05 x̃: 2
    helped stats (rel) min: 0.02% max: 3.82% x̄: 0.61% x̃: 0.46%
    HURT stats (abs)   min: 1 max: 134 x̄: 4.69 x̃: 2
    HURT stats (rel)   min: <.01% max: 5.59% x̄: 0.65% x̃: 0.44%
    95% mean confidence interval for instructions value: 0.13 0.83
    95% mean confidence interval for instructions %-change: <.01% 0.08%
    Instructions are HURT.

    total cycles in shared programs: 809326677 -> 809475669 (0.02%)
    cycles in affected programs: 447781659 -> 447930651 (0.03%)
    helped: 1924
    HURT: 1994
    helped stats (abs) min: 1 max: 74567 x̄: 1217.49 x̃: 10
    helped stats (rel) min: <.01% max: 38.44% x̄: 1.09% x̃: 0.17%
    HURT stats (abs)   min: 1 max: 76426 x̄: 1249.47 x̃: 8
    HURT stats (rel)   min: <.01% max: 137.11% x̄: 1.64% x̃: 0.17%
    95% mean confidence interval for cycles value: -125.61 201.67
    95% mean confidence interval for cycles %-change: 0.12% 0.48%
    Inconclusive result (value mean confidence interval includes 0).

    LOST:   4
    GAINED: 4

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24104>
 2023-07-19 02:11:57 +00:00
Eric Engestrom
0f557ffa26 ci: move lavapipe files rules to src/gallium/drivers/lavapipe/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
a15384383b ci: move softpipe files rules to src/gallium/drivers/softpipe/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
14b9f460c2 ci: move llvmpipe files rules to src/gallium/drivers/llvmpipe/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
96344c7b71 ci: move virgl files rules to src/gallium/drivers/virgl/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
5828d86c26 ci: move zink files rules to src/gallium/drivers/zink/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
58077c6add ci: move lima files rules to src/gallium/drivers/lima/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
Eric Engestrom
8b8169f52e ci: move nouveau files rules to src/gallium/drivers/nouveau/ci/gitlab-ci.yml 
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24099>
 2023-07-18 23:07:52 +00:00
David Rosca
e6f0819806 radeonsi/vcn: Enable full/limited range support for H264/HEVC/AV1 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
756e5d6687 radeonsi/vcn: Set HEVC video signal parameters in bitstream 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
f44697239d radeonsi/vcn: Set H264 video signal parameters in bitstream 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
8a21efce3a frontends/va: Add postproc support for converting to full range 
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:34 +00:00
David Rosca
8438d6363a frontends/va: Parse HEVC SPS for video signal parameters 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:33 +00:00
David Rosca
2785d54b71 frontends/va: Parse H264 SPS for video signal parameters 
Since packed headers support is now advertised for H264,
it also fixes encoding into mkv with ffmpeg.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3524

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24174>
 2023-07-18 21:40:33 +00:00
David Rosca
cfd24047a1 radeonsi/vcn: Don't use chroma in AV1 encode with RGB input 
Fixes: 64eab1f3ae

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24170>
 2023-07-18 20:09:42 +00:00
David Rosca
2cb4c6aef0 frontends/va: Don't use EFC with scaling or filtering enabled 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24170>
 2023-07-18 20:09:42 +00:00
David Rosca
b5fa9f992d frontends/va: Skip processing buffers already converted with EFC 
Since the EFC conversion reallocates the dst buffer with new format,
any subsequent VA postproc calls on the same surface will fall back
to vl_compositor conversion.

This is the case in ffmpeg where the postproc filter output
buffers are reused instead of allocated for each frame.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24170>
 2023-07-18 20:09:42 +00:00
Kenneth Graunke
283e3acd3a iris: Re-emit 3DSTATE_DS for each primitive (workaround 14019750404) 
Some platforms require us to re-emit 3DSTATE_DS before every 3DPRIMITIVE
when tessellation is enabled.  See workaround 14019750404.

Cc: 23.2 <mesa-stable>

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24150>
 2023-07-18 19:14:27 +00:00
Iván Briano
50d68f74b5 iris: ensure mesh is disabled on context init 
It turns out the hardware doesn't save the whole state on a context
switch, as the kernel expects when it creates the golden context.
For some HW units, only the state that was explicitly programmed will be
part of it, so we need to make sure mesh shading is disabled on context
creation, or we risk being context switched with an application that
uses mesh, and when ours gets to run again, the mesh state won't be
reset, and submitting a legacy 3D pipeline while the HW thinks mesh is
enabled causes us to hang.

Cc: 23.2 <mesa-stable>

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24150>
 2023-07-18 19:14:27 +00:00
Gert Wollny
f48aa460a2 r600/sfn: Print more info if scheduling fails 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
2a9348967a r600/sfn: Add some tests for proper register access 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
382e198503 r600/sfn: reorder the value factory class member declaration a bit 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00
Gert Wollny
00417c216e r600/sfn: Add peephole optimization to move a dest to the previous op 
This is mostly tailored to the register store op where we get a sequence

   ALU OP S1.x : ...
   ALU MOV R1.x = S1.x

but it can help elsewhere too.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24212>
 2023-07-18 17:51:47 +00:00