Commit graph

216781 commits

Author SHA1 Message Date
Carlos Santa
3b8fb95fec intel/hang_replay: add option to dump VM state as part of the dump
Replaying a dump file requires the VM state in order to feed the
replay tool with the necessary VMA properties that described the hang,
however, these properties are not necessarily useful once the replay
tool re-runs said traces, however, this patch makes this optional.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34829>
2026-01-07 19:16:25 +00:00
Carlos Santa
d1cad0da82 intel/hang_replay: add Xe support
The tool now can seamlessly support GPU hang dump files from
either the i915 or the Xe drivers.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34829>
2026-01-07 19:16:25 +00:00
Carlos Santa
c8a08c5375 intel/tools: Handle new replay properties in the Xe KMD error dump file
The changes as part of the Contexts state now include:

**** Contexts ****
[HWCTX].replay_offset: 0x0
[HWCTX].replay_length: 0xd000

and the changes as part of the VM state now include:

**** VM state ****
VM.uapi_flags: 0x1
[40000].length: 0x2000
[40000].properties: read_write|bo|mem_region=0x1|pat_index=2|cpu_caching=1
[40000].data: &-)\3!!E9mzzzzzzzzzz

In order to be able to replay a GPU hang from a devcore dump file
new properties have been added describing the offset and the length
of the affected hw context as well as a global VM flag and
several VMA property types: memory region, bo caching, pat index,
memory permission and memory type.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34829>
2026-01-07 19:16:25 +00:00
Carlos Santa
fdb1948410 intel/hang_replay: move common code into a lib
Before bringing support for Xe let's create a lib so that
the common code can live there.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34829>
2026-01-07 19:16:25 +00:00
Carlos Santa
77337b04cb intel/tools: intel_hang_replay refactoring
initial refactoring of the i915 code in preparation
for Xe. No functional changes.

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34829>
2026-01-07 19:16:25 +00:00
Christian Gmeiner
6a42493c94 pvr: Use BUILD_ID_EXPECTED_HASH_LENGTH
SHA1_DIGEST_LENGTH was changed to refect BLAKE3 exposed with SHA1 functions - switch
to BUILD_ID_EXPECTED_HASH_LENGTH.

Fixes: 492a176cbb ("util: increase SHA1_DIGEST_LENGTH to 32 (BLAKE3_KEY_LEN)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39192>
2026-01-07 18:38:56 +00:00
Danylo Piliaiev
be190a5d3d tu: Fix passing tmp arrays to tu_desc_set_swiz/fdl6_buffer_view_init
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../src/freedreno/vulkan/tu_clear_blit.cc:3664:1:   required from here
../src/freedreno/vulkan/tu_clear_blit.cc:1274:26: error: taking address of temporary array
 1274 |    tu_desc_set_swiz<CHIP>(desc, tu_swiz(X, Y, Z, W));

Fixes: 75166dff1d ("tu: Extract out descriptor helpers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39198>
2026-01-07 16:43:31 +00:00
Faith Ekstrand
71310a54c5 pan/genxml: Get rid of non-existant Tiler Heap fields
These only really exist on v9 and are gone starting with v10.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39182>
2026-01-07 16:22:21 +00:00
José Roberto de Souza
e46d955db2 anv: Set push_constant_range once
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That whole comment about Ivy Bridge is not relevant as ANV don't support IVB.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39175>
2026-01-07 14:25:43 +00:00
José Roberto de Souza
cf3c02ab30 anv: Fix variable shadowing
There is no side affects for this shadowing but better fix it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39175>
2026-01-07 14:25:43 +00:00
José Roberto de Souza
0cc73385e6 intel/brw: Document UBO_START
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39175>
2026-01-07 14:25:42 +00:00
José Roberto de Souza
961ca451e0 intel/brw: Add comment to ubo_ranges
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39175>
2026-01-07 14:25:42 +00:00
Pierre-Eric Pelloux-Prayer
a123fb9dec ci: enable shader-db test for radeonsi
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Acked-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38712>
2026-01-07 10:55:48 +00:00
Pierre-Eric Pelloux-Prayer
68ef044b3b Revert "glthread: mark internal bufferobjs for the ctx they belong to"
This reverts commit 45b6aa1eb7.

This is not thread safe and will lead to buffer leaks, eg:

[threadA] _mesa_reference_buffer_object_       ctx=0x60bc07fa33f0 buf=0x60bc09b90020 CtxRefCount-=993187
[threadB] _mesa_glthread_release_upload_buffer ctx=0x60bc07fa33f0 buf=0x60bc09b90020 ref=7768 CtxRefCount=993212 -> 954
[threadB] _mesa_glthread_upload                ctx=0x60bc07fa33f0 buf=0x60bc09eb7d00 CtxRefCount=1000000
[threadA] _mesa_reference_buffer_object_       ctx=0x60bc07fa33f0 buf=0x60bc09b90020 CtxRefCount-=993186
 ../src/mesa/main/bufferobj.h:201: _mesa_reference_buffer_object_: Assertion `oldObj->Ctx == ctx' failed.

The assert is one added by the previous commit.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14483
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39036>
2026-01-07 10:19:50 +00:00
Pierre-Eric Pelloux-Prayer
090f4d9a5d mesa: add assert to validate the no atomic path
Comparing the ctx values and then updating the refcounts is not
thread-safe so add an assert to make sure the ctx wasn't updated
by another thread (via detach_ctx_from_buffer).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39036>
2026-01-07 10:19:50 +00:00
Georg Lehmann
a706769a0b nir: move exact bit to nir_fp_math_control
Unifies nir per instruction float control.

In the future this can be split into contract/reassoc/transform
like SPIR-V.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (except SPIR-V)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:57 +00:00
Georg Lehmann
ce27703768 spirv: don't set float control for integer dot
As the name says, integer dot products do not operate on floats.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:57 +00:00
Georg Lehmann
eb4737a1dd nir: add nir_alu_instr_is_exact helper
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:57 +00:00
Georg Lehmann
b70294b91f nir: document signed zero, inf, nan preserve flags
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:56 +00:00
Georg Lehmann
9d027fc870 nir/opt_varyings: actually clone alu math control to different shader
Cc: mesa-stable

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39103>
2026-01-07 09:40:56 +00:00
Eric Engestrom
93390d4b73 vk/runtime,zink: only integrate renderdoc on supported platforms
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It is not actually available to all the platforms mesa can be compiled
to, so let's keep an opt-in list of supported platforms instead, and
compile it out on all other platforms.

Fixes: 48a0478126 ("zink: add renderdoc handling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39176>
2026-01-07 09:08:46 +00:00
Eric Engestrom
f009ee9bfd Revert "renderdoc: Add Haiku platform support"
This reverts commit a1a1ff7e57.

This was the wrong fix; see discussion on
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39130

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39176>
2026-01-07 09:08:46 +00:00
Marek Olšák
60e94e2b81 util: remove SHA1, use BLAKE3 in its functions to switch everything to BLAKE3
This is the least invasive way to switch all of Mesa to BLAKE3. It's done
this way for transitional reasons.

SHA1_DIGEST_LENGTH is already equal to BLAKE3_KEY_LEN. This just switches
the SHA1 implementation to BLAKE3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39110>
2026-01-07 08:32:33 +00:00
Marek Olšák
492a176cbb util: increase SHA1_DIGEST_LENGTH to 32 (BLAKE3_KEY_LEN)
The last 12 bytes are always 0 for now. With this, all SHA1 functions
can be internally implemented as BLAKE3, so that we can switch everything
to BLAKE3 by only changing the implementation of the sha1 utility.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39110>
2026-01-07 08:32:33 +00:00
Marek Olšák
524a536b7b util: use SHA1_DIGEST_STRING_LENGTH in fossilize_db
preparation for changing SHA1_DIGEST_LENGTH to BLAKE3_KEY_LEN

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39110>
2026-01-07 08:32:33 +00:00
Marek Olšák
9e64713500 anv: use SHA1_DIGEST_LENGTH
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39110>
2026-01-07 08:32:33 +00:00
Marek Olšák
0b7ee3b981 ALL: use #define and a copy helper to check and copy build_id
preparation for changing SHA1_DIGEST_LENGTH to BLAKE3_KEY_LEN

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39110>
2026-01-07 08:32:33 +00:00
Marek Olšák
1912a00a91 ALL: use SHA1_DIGEST_LENGTH etc. instead of hardcoding the numbers
only build_id is switched to use literal 20 instead of SHA1_DIGEST_LENGTH
because we will increase SHA1_DIGEST_LENGTH to BLAKE3_KEY_LEN

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39110>
2026-01-07 08:32:33 +00:00
Samuel Pitoiset
9f5dd888b6 radv/sqtt: add a comment about the allocation strategy of the SQTT BO
Some checks are pending
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39172>
2026-01-07 06:57:29 +00:00
Samuel Pitoiset
ffa343ed05 Revert "radv: allocate the SQTT BO in GTT for faster readback"
This reverts commit da07f1ef3f.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14591
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39172>
2026-01-07 06:57:29 +00:00
Ian Forbes
58303e5d2d svga: Set modifier in surface_get_handle
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Without this hardware cursors will not work on wlroots based compositors.
Only MOD_LINEAR is supported by the device.

Signed-off-by: Ian Forbes <ian.forbes@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39168>
2026-01-06 22:06:44 +00:00
Emma Anholt
1e8a1e9285 nir/algebraic: Apply autopep8.
I needed to reformat the nir_algebraic unit test generation, but we
weren't in pep8 to begin with.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:49 +00:00
Konstantin Seurer
e2ac22a068 nir: Allow using nir_eval_const_opcode in C++ code
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:49 +00:00
Konstantin Seurer
295b67f7bf nir: Allow shaders in tests to be annotated
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:49 +00:00
Konstantin Seurer
2ed16ed1a6 nir/print: Print annotations as comments
Also prints them in the same line as the instruction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:49 +00:00
Georg Lehmann
17615b412b nir: prevent undefined behavior in idiv/imod/irem constant folding
Prevents SIGFPE when doing constant evaluation in the upcoming
nir_opt_algebraic_pattern_tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:49 +00:00
Emma Anholt
feffd0e445 nir: Avoid UB of (int)0xff << 24 evaluating usadd_4x8_vc4.
Caught by UBSan on introduction of nir_opt_algebraic_pattern_test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:49 +00:00
Konstantin Seurer
a8224e3e00 nir/opt_algebraic: Do not emit patterns for 64bit booleans
Avoids assertion failures trying to constant-evaluate the pattern with the
new nir_opt_algebraic_pattern_tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:48 +00:00
Konstantin Seurer
211c7db8e3 nir/opt_algebraic: Remove a pattern for 8bit floats
Avoids assertion failures trying to constant-evaluate the pattern with the
new nir_opt_algebraic_pattern_tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:48 +00:00
Emma Anholt
afece95101 nir/opt_algebraic: Fix return type of fdot(vec(a, 0.0, ...), b).
The replace pattern was generating a vector when it should have been
scalar.  Fixes validation failures with the new algebraic unit tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39184>
2026-01-06 21:27:47 +00:00
Marek Olšák
13cfd0176c ac/gpu_info: add #define AMD_MEMCHANNEL_INTERLEAVE_BYTES
radeon_info::pipe_interleave_bytes is renamed to r600_pipe_interleave_bytes
where it can be 512 on some chips.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39120>
2026-01-06 20:32:10 +00:00
Marek Olšák
92133bb0ab amd: demystify various optimizations we already have for memory channels
Explain why we do what we do, and use the radeon_info field properly.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39120>
2026-01-06 20:32:10 +00:00
Rob Clark
75166dff1d tu: Extract out descriptor helpers
Some checks are pending
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Turnip has to build/munge descriptors in a bunch of places.  Extract out
helpers so we don't have to duplicate the gen8 vs earlier descriptor
format changes everywhere.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39141>
2026-01-06 20:06:05 +00:00
Rob Clark
c34d5ad6a4 tu: Use more fdl6_buffer_view_init()
Remove some open coded descriptor building to simplify adding gen8
descriptor support.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39141>
2026-01-06 20:06:05 +00:00
Rob Clark
199d5568d5 tu: Plumb CHIP thru descriptor set building
The descriptor format changes in gen8, which is mostly abstracted by
the fdl helpers.  But to utilize that we need to plumb the CHIP thru
12 layers for different ways of vk doing the same thing.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39141>
2026-01-06 20:06:05 +00:00
Rob Clark
6f6880bcac tu: Replace A6XX_TEX_CONST_DWORDS
Fortunately the descriptor size is the same on gen8.  But use the
generic define anyways.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39141>
2026-01-06 20:06:05 +00:00
Rob Clark
34944f85cd freedreno/fdl: Add STRUCTSIZETEXELS arg
Turnip needs this for accel structures.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39141>
2026-01-06 20:06:05 +00:00
Rob Clark
6db51151b5 freedreno/fdl: Fix gen8 buffer descriptors
DEPTH field is actually STRUCTSIZETEXELS.  And for buffers the iova only
needs to be byte aligned, replacing STARTOFFSETTEXELS on a6xx/a7xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39141>
2026-01-06 20:06:05 +00:00
Mel Henning
5fa1e5707b util/rmq: Remove unused header
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39165>
2026-01-06 19:17:03 +00:00
Mel Henning
4171161227 util/rmq: Fix uninitialized read in preprocess
We were previously always reading table->width elements from the previous
row in this loop, but we write fewer entries than that to the current
row. Fix this by adjusting the element count.

Fixes: 0d07b86073 ("util: Add range_minimum_query")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14593
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39165>
2026-01-06 19:17:03 +00:00