fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 16:08:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2
133663 commits 66 branches 933 tags 991 MiB
Commit graph

133663 commits

This branch
This branch
All branches
Author SHA1 Message Date
Alyssa Rosenzweig
3a16ab84e2 pan/bi: Fix RA of node 0 
Fixes: 39aa8c4a5a ("pan/bi: Switch to new IR")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig
92461a1133 pan/bi: Fix 64-bit SSBO addresses 
Fixes: 9c7efc4510 ("pan/bi: Add intrinsic emits for builder")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
a8c91f15f0 pan/mdg: Fix spilling when scratch memory is used 
Add the tls_size from NIR before spilling so that it doesn't alias
with spill slots.

Fixes: 152bc5d15e ("pan/mdg: Support loads and stores to scratch memory")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
6f0eff548c pan/bi: Implement packing ops between 32-bit vec1 and 16-bit vec2 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
c9c637a707 pan/bi: Implement ihadd/irhadd operations 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
591ccbcf47 pan/bi: Implement saturated add/sub operations 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
7258b4b48d panfrost: Set TLS for compute jobs 
Fixes CL programs using scratch storage, such as the Piglit test
i32-stack-array.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
3f7e7495fc pan/bi: Lower umul_high 
Also lower uadd_carry, which the mul_high lowering generates.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
2e372d0c3b pan/bi: Add w0 to the 'h01' swizzle bucket 
A number of instructions, such as LOAD.i8, use this swizzle in the XML.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
2ec0897b11 pan/mdg: Allow 64-bit src_bitsize for comparison operations 
Fixes Piglit test attributes.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
b5d6e5049f pan/mdg: Don't reorder loads/stores past each other 
Fixes Piglit test local-memory.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
24fcc032ef pan/mdg: Limit int64 vectorization 
Previously, nir_opt_vectorize was sometimes vectorizing 64-bit
load_const instructions to vec4.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
f0109e9ac0 panfrost: Assert on sysval overflow 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
24867386ee panfrost: Add a sysval for local_work_dim 
Fixes Piglit test get-work-dim.cl.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
f5a35918db panfrost: Add a sysval for local_group_size 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
76fa57d195 pan/bi: Use pan_nir_lower_64bit_intrin 
The intrinsics covered by the pass are implemented by reading 32-bit
registers, so there is no reason to keep them 64-bit.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
7c2308769b panfrost: Use the correct NIR options for OpenCL on Bifrost 
This is needed so that 64-bit operations are lowered properly.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
c82ab9b94a pan/bi: Improve unknown intrinsic error 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
56f753f8e2 panfrost: Set bifrost_props for compute shaders 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
c71d4d931e pan/bi: Implement load_kernel_input 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
f33694552d pan/bi: Implement load/store intrinsics 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
58cf95a637 pan/bi: Improve interoperability of the command-line disassembler 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
7c6aa5f49d pan/bi: Set compute lowering options 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
d267183829 pan/bi: Add some compute intrinsic loads 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
2a7c33bd9d pan/bi: Handle 64-bit pack and unpack operations 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Icecream95
f5c9a10f33 pan/bi: Lower 64-bit integers 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Alyssa Rosenzweig
f4d2b35ac8 pan/bi: Pipe scratch_size in from NIR 
Needs to be added to whatever we spill ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
 2021-01-18 20:49:45 +00:00
Ilia Mirkin
087ef91c85 nvc0: index_bias is now only set for indexed draws 
Fixes: cbdc00ac3a ("nouveau: fix handling draw info")
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8539>
 2021-01-18 17:51:58 +00:00
Ilia Mirkin
111c0733ea cso: set index_bounds_valid = true for arrays draws 
The min/max indices are valid. Set the bit to true to indicate that.

Fixes glClear (+ clear_with_quads) on nouveau.

Fixes: 72ff53098c (gallium: add pipe_draw_info::index_bounds_valid)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reported-by: Simon Ser <contact@emersion.fr>
Tested-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8546>
 2021-01-18 17:33:52 +00:00
Erik Faye-Lund
333730405d zink: handle NULL views in zink_set_sampler_views 
Passing NULL for the views parameter should be the same as passing an
array of NULL, according to the documentation. So let's respect that
detail.

This fixes a crash when using GALLIUM_HUD.

Fixes: 8d46e35d16 ("zink: introduce opengl over vulkan")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8564>
 2021-01-18 17:06:12 +00:00
Samuel Iglesias Gonsálvez
b50b28cd33 turnip: disable UBWC on Z24_S8 MSAA images on A630 
Fixes GPU hangs in dEQP-VK.renderpass2.depth_stencil_resolve.* tests
on A630.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8381>
 2021-01-18 17:32:21 +01:00
Jason Ekstrand
63a431b81c anv: Add a trivial implementation of VK_KHR_deferred_host_operation 
This isn't actually capable of deferring anything; it just trivially
returns success.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7735>
 2021-01-18 10:09:51 -06:00
Bas Nieuwenhuizen
af1aef10f9 radv: Do not use a pipe offset for aliased sparse images. 
Otherwise the offset might not match between the images that are
aliased.

Fixes: e553ea51e8 ("radv: Create sparse images.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4072
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8535>
 2021-01-18 11:12:45 +00:00
Michel Dänzer
23f2e77710 wsi/x11: Use get_screen_resources_current in wsi_x11_detect_xwayland 
get_screen_resources may trigger an active probe of display connections
in the X server, which may take significant time and/or result in log
file spam.

Fixes: b5268d532a "wsi/x11: Detect Xwayland"
Reported-by: Sylvain Bertrand <sylvain.bertrand@legeek.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8492>
 2021-01-18 10:03:32 +00:00
Marek Olšák
b06f3c52bf radeonsi: trim the size of si_vgt_param_key and si_vgt_stages_key 
These are the minimum sizes we can use.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
f1e34f125d radeonsi: don't use si_get_vs_state in most places 
It's incorrect because si_get_vs_state returns gs_copy_shader for legacy
GS. It was harmless, but let's use si_get_vs, which is simpler.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
4088b6f293 radeonsi: rearrange condition for streamout workaround on gfx7 and gfx8 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
eb22bd2072 radeonsi: get out of si_emit_vs_state early for blit vertex shaders 
They don't use current_vs_state.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
73709143d2 radeonsi: remove MRT-draw-calls, spill-draw-calls, spill-compute-calls 
due to limited usefulness and overhead in si_draw_vbo.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
f2a5148701 radeonsi: make sctx->vertex_elements always non-NULL 
Bind a state with 0 vertex elements there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
961aa67adf radeonsi: add a specialized function for CP DMA L2 prefetch 
This radically simplifies the code to decrease CPU overhead in si_draw_vbo.
The generic CP DMA copy function is too complicated.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
0eca4660a5 radeonsi: make cik_emit_prefetch_L2 templated and move it to si_state_draw.cpp 
This is a great candidate for a template. There are a lot of conditions
that are already templated in si_draw_vbo.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
c43d00dc91 radeonsi: fix si_num_prims_for_vertices for PIPE_PRIM_POLYGON 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
6682c1603c radeonsi: don't compute average vertex count in si_draw_vbo 
It's probably not needed and we also have draw merging on gfx10,
so we should be able to use total_driver_count in theory.
(I may be wrong, but I don't know if having avg_direct_count really
improves anything)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
295106c3e7 radeonsi: don't pass pipe_draw_info into si_emit_derived_tess_state 
Only one field is used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
6f74105a34 radeonsi: translate pipe_prim_type only when it changes 
just sink it into the branch

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
d0d4c4ba1d radeonsi: don't pass pipe_draw_info into si_emit_ia_multi_vgt_param 
Only one field is used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
53f9bb860b radeonsi: don't pass pipe_draw_info into si_emit_vs_state 
only one field is used

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
4056e953fe radeonsi: move emit_cache_flush functions into si_gfx_cs.c 
This is a better place for them. They are not inlined anyway.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00
Marek Olšák
1ceec51b12 radeonsi: don't clear unaligned bits when unbinding vertex buffers 
It's initialized to 0, so &= is a no-op.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8548>
 2021-01-18 01:17:19 +00:00