Commit graph

76907 commits

Author SHA1 Message Date
Kenneth Graunke
9f0944d15b i965: Make TES inputs match TCS outputs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:29 -08:00
Kenneth Graunke
4fac950010 i965: Force VS -> TCS varyings to use the SSO VUE map layout.
The compact VUE map only works when varying packing is in use.
Unfortunately, varying packing is disabled for TCS inputs.

This is needed to fix Piglit's tcs-input-read-array-interface test.

v2: Make lines fit in 80 columns (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:18 -08:00
Kenneth Graunke
bee42cc1f7 i965: Handle TCS outputs and TES inputs.
TCS outputs and TES inputs both refer to a common "patch URB entry"
shared across all invocations.  First, there are some number of
per-patch entries.  Then, there are per-vertex entries accessed via
an offset for the variable and a stride times the vertex index.

Because these calculations need to be done in both the vec4 and scalar
backends, it's simpler to just compute the offset calculations in NIR.
It doesn't necessarily make much sense to use per-vertex intrinsics
afterwards, but that at least means we don't lose the per-patch vs.
per-vertex information.

v2: Use is_input/is_output helpers (suggested by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:13 -08:00
Kenneth Graunke
31140d097a i965: Handle TCS inputs and TES outputs.
TES outputs work exactly like VS outputs, so we can simply add a case
statement for those.

TCS inputs are very similar to geometry shaders - they're arrays of
per-vertex data.  We use the same method I used for the scalar GS
backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:07 -08:00
Kenneth Graunke
1f46163acb i965: Add tessellation shader VUE map code.
Based on a patch by Chris Forbes, but largely rewritten by Ken.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-14 14:48:01 -08:00
Kenneth Graunke
9f3917bf37 i965: Fix partial variable access for geometry shaders in SSO mode.
Without varying packing, if a VS writes a compound variable, and the GS
only reads part of it, the base location of the variable may not
actually be in the VUE map.

To cope with this, we do lowering in terms of varying slots, add any
constant offsets to the base, and then do the VUE map remapping.  This
ensures we only look up VUE map entries for slots which actually exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:39:38 -08:00
Kenneth Graunke
8c4deb10df i965: Separate base offset/constant offset combining from remapping.
My tessellation branch has two additional remap functions.  I don't want
to replicate this logic there.

v2: Handle inputs/outputs separately (suggested by Jason Ekstrand).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:39:34 -08:00
Kenneth Graunke
106c3a8a48 nir: Fix number of indices on shared variable store intrinsics.
Shared variables and input reworks landed around the same time.
Presumably, this was some sort of mistake in rebase conflict resolution.

This really only affects the num_indices field in nir_intrinsic_infos,
which is rarely used.  However, it's used by the printer.

Found by inspection.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-14 14:27:38 -08:00
Jason Ekstrand
dba28da075 anv/buffer_view: Store a bo + offset instead of buffer pointer
This is what image_view does.  Also, we really need to do this so that we
can properly handle the combined offsets from the buffer and from
pCreateInfo.

This fixes some of the nonzero offset buffer view CTS tests.
2015-12-14 14:10:40 -08:00
Ian Romanick
96dc732ed8 meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER
GL_DRAW_FRAMEBUFFER does not exist in OpenGL ES 1.x, and since
_mesa_meta_begin hasn't been called yet, we have to work-around API
difficulties.  The whole reason that GL_DRAW_FRAMEBUFFER is used instead
of GL_FRAMEBUFFER is that the read framebuffer may be different.  This
is moot in OpenGL ES 1.x.

I have another patch series that would also fix this (by removing the
calls to _mesa_BindFramebuffer and friends), but it's not quite ready
yet... and I think it may be a bit heavy for some stable branches.
Consider this a stop-gap fix.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93215
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-12-14 13:09:15 -08:00
Chad Versace
ee57062e1e anv: Remove anv_image::surface_type
When building RENDER_SURFACE_STATE, the driver set
SurfaceType = anv_image::surface_type, which was calculated during
anv_image_init(). This was bad because the value of
anv_image::surface_type was taken from a gen-specific header,
gen8_pack.h, even though the anv_image structure is used for all gens.

Replace anv_image::surface_type with a gen-specific lookup function,
anv_surftype(), defined in gen${x}_state.c.

The lookup function contains some useful asserts that caught some nasty
bugs in anv meta, which were fixed in the previous commit.
2015-12-14 10:46:27 -08:00
Samuel Pitoiset
71135e275f nvc0: check return value of nvc0_program_validate()
Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-14 19:08:42 +01:00
Samuel Pitoiset
54f58210c2 nv50: check return value of nouveau_object_new()
When ret == 0, obj is not NULL. Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-14 19:08:39 +01:00
Samuel Pitoiset
3f7462b792 nv50,nvc0: make use of unreachable() when invalid texture target happens
Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-14 19:08:25 +01:00
Chad Versace
f0d11d5a81 anv/meta: Fix VkImageViewType
Meta unconditionally used VK_IMAGE_VIEW_TYPE_2D in the functions below.
This caused some out-of-bound memory accesses.
  anv_CmdCopyImage
  anv_CmdBlitImage
  anv_CmdCopyBufferToImage
  anv_CmdClearColorImage

Fix it by adding a new function, anv_meta_get_view_type().
2015-12-14 09:03:58 -08:00
Chad Versace
0bebaeacd7 isl: Rename s/lod_align/image_align/ for consistency
Regarding the subimages within a surface, sometimes isl called them
"images" and sometimes "LODs". This patch make isl consistently refer to
them as "images".  I choose the term "image" over "LOD" because LOD is
an misnomer when applied to 3D surfaces. The alignment applies to each
individual 2D subimage, not to the LOD as a whole.

This patch changes no behavior. It's just a manually performed,
case-insensitive, replacement s/lod/image/ that maintains correct
indentation.  any behavior.
2015-12-14 09:01:51 -08:00
Chad Versace
85a6384014 anv/tests: gitignore block_pool_no_free 2015-12-14 09:00:28 -08:00
Chad Versace
0da776b733 anv: Fix build for unit tests
Clearly no one has been running `make check`, because the unittestbuild
has been broken for a long time. After this buildfix, all tests now
pass.
2015-12-14 09:00:28 -08:00
Christian König
8b52fa71ac st/va: handle default post process regions
Avoid referencing NULL pointers.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:55 +01:00
Christian König
f6dd31c1cf st/va: fix unused variable warning
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:55 +01:00
Christian König
025d97381e st/va: clean up post process includes
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:54 +01:00
Christian König
27a276f625 st/va: cleanup filter color standard handling
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: ulien Isorce <j.isorce@samsung.com>
2015-12-14 11:54:54 +01:00
Tapani Pälli
8b79258cfe meta: clear_state structure cleanup
Remove unused variables from clear_state and use a hardcoded location
for color uniform to get rid of 2 more variables. Modify shaders to use
explicit location for vertex attribute too as extension is enabled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-14 08:01:49 +02:00
Ilia Mirkin
eca8f38dcf glsl: assign varying locations to tess shaders when doing SSO
GRID Autosport uses SSO shaders. When a tessellation evaluation shader
is passed through this, it triggers assertion failures down the line
with unassigned varying locations. Make sure to do this when the first
shader in the pipeline is not a vertex shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-13 11:35:28 -05:00
Neil Roberts
839793680f i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals
Previously if the visual didn't have an alpha channel then it would
pick a format that is not sRGB-capable. I don't think there's any
reason not to always have an sRGB-capable visual. Since 28090b30 there
are now visuals advertised without an alpha channel which means that
games that don't request alpha bits in the config would end up without
an sRGB-capable visual. This was breaking supertuxkart which assumes
the winsys buffer is always sRGB-capable.

The previous code always used an RGBA format if the visual config
itself was marked as sRGB-capable regardless of whether the visual has
alpha bits. I think we don't actually advertise any sRGB-capable
visuals (but we just use sRGB formats anyway) so it shouldn't make any
difference. However this patch also changes it to use RGBX if an
sRGB-capable visual is requested without alpha bits for consistency.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-13 14:29:42 +00:00
Neil Roberts
43f4be5f06 i965: Add B8G8R8X8_SRGB to the alpha format override
brw_init_surface_formats overrides the render format for RGBX formats
which aren't supported for rendering so that they internally use RGBA
instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a
renderable format. This patch just adds it.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-13 14:29:41 +00:00
Neil Roberts
c769efda93 i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
This will be used in a subsequent patch as the format for RGB visuals.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-13 14:29:38 +00:00
Jason Ekstrand
c56186026f anv: Add initial support for texel buffers 2015-12-12 16:11:23 -08:00
Jason Ekstrand
fd944197f2 i965/nir: Provide a default LOD for buffer textures
Our hardware requires an LOD for all texelFetch commands even if they are
on buffer textures.  GLSL IR gives us an LOD of 0 in that case, but the LOD
is really rather meaningless.  This commit allows other NIR producers to be
more lazy and not provide one at all.
2015-12-12 16:09:54 -08:00
Ilia Mirkin
7752bbc44e gk104/ir: simplify and fool-proof texbar algorithm
With the current algorithm, we only look at tex uses. However there's a
write-after-write hazard where we might decide to, on some path, not use
a texture's output at all, but instead to write a different value to
that register. However without the barrier, the texture might complete
later and overwrite that value.

This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x,
and likely other random-looking failures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-12-12 18:10:16 -05:00
Ilia Mirkin
d35695096d nv50/ir: combine sequences of conversions
In some cases shaders want non-default rounding when converting float to
integer. This can be done in one go, so merge the two ops. This comes up
in the packUnorm4x8 & co functions, as well as a few random shaders.
Overall shader-db impact is minimal, helping a handful of witcher2 and
other misc shaders.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:16 -05:00
Ilia Mirkin
dbca0f3eba nv50/ir: manually optimize multiplication expansion logic
The conversion of 32-bit integer multiplies into 16-bit ones happens
after the regular optimization loop. However it's fairly common to
multiply by a small integer, rendering some of the expansion pointless.

Firstly, propagate immediates when possible into mul ops, secondly just
remove the ops when they are unnecessary.

Including the change to generate imad immediates, the effect is:

total instructions in shared programs : 6365463 -> 6351898 (-0.21%)
total gprs used in shared programs    : 728684 -> 728684 (0.00%)
total local used in shared programs   : 9904 -> 9904 (0.00%)
total bytes used in shared programs   : 44001576 -> 44036120 (0.08%)

                local        gpr       inst      bytes
    helped           0           0        3288           4
      hurt           0           0           0         842

It's easy for this to hurt bytes since we end up always generating the
8-byte form, while we can't always get rid of the immediate in question.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:16 -05:00
Ilia Mirkin
3af83c4bc7 nv50/ir: fix imul emission in the presence of an immediate
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin
a0b5d5beed nv50/ir: teach post-ra immediate folding into mad about integers
There will usually be a split before the mad op, peer through that and
pick out the right word of the immediate.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin
ab70ea1353 nv50/ir: add short imad support
Support emission of the short imad, but also include it in the various
logic that tries to make it possible to emit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin
6aca7fecb7 nv50/ir: can't have predication and immediates
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-12 18:10:15 -05:00
Ilia Mirkin
69e8b476d0 nv50/ir: fix texture grad for cubemaps
We were ignoring the partial derivatives on the last dim.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Ilia Mirkin
a27548400e nv50/ir: fix assumption that prog->maxGPR is in 32-bit reg units
On NV50, we use 16-bit reg units (to make it all work with half-regs). A
few places assumed that it was always in 32-bit units.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-12 18:10:15 -05:00
Nicolai Hähnle
d640f179d3 gallium/ddebug: regularly log the total number of draw calls
This helps in the use of GALLIUM_DDEBUG_SKIP: first run a target application
with skip set to a very large number and note how many draw calls happen
before the bug. Then re-run, skipping the corresponding number of calls.
Despite the additional run, this can still be much faster than not skipping
anything.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-12 15:23:50 -05:00
Nicolai Hähnle
b86d5ccae2 gallium/ddebug: add GALLIUM_DDEBUG_SKIP option
When we know that hangs occur only very late in a reproducible run (e.g.
apitrace), we can save a lot of debugging time by skipping the flush and hang
detection for earlier draw calls.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-12 15:23:34 -05:00
Roland Scheidegger
af7ba989fb llvmpipe: fix layer/vp input into fs when not written by prior stages
ARB_fragment_layer_viewport requires that if a fs reads layer or viewport
index but it wasn't output by gs (or vs with other extensions), then it reads
0. This never worked for llvmpipe, and is surprisingly non-trivial to fix.
The problem is the mechanism to handle non-existing outputs in draw is rather
crude, it will simply redirect them to whatever is at output 0, thus later
stages will just get garbage. So, rather than trying to fix this up (which
looks non-trivial), fix this up in llvmpipe setup by detecting this case there
and output a fixed zero directly.
While here, also optimize the hw vertex layout a bit - previously if the gs
outputted layer (or vp) and the fs read those inputs, we'd add them twice
to the vertex layout, which is unnecessary.
And do some minor cleanup, slots don't require that many bits, there was some
bogus (but harmless) float/int mixup for psize slot too, make the slots all
unsigned (we always put pos at pos zero thus everything else has to be positive
if it exists), and make sure they are properly initialized (layer and vp index
slot were not which looked fishy as they might not have got set back to zero
when changing from a gs which outputs them to one which does not).

This fixes the failures in piglit's arb_fragment_layer_viewport group
(3 each for layer and vp).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-12 01:59:15 +01:00
Brian Paul
27d5be0b8f svga: avoid emitting redundant SetSamplers() commands
This greatly reduces the number of SetSamplers() commands for some
applications.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2015-12-11 16:54:58 -07:00
Brian Paul
1291e910d5 svga: avoid emitting redundant SetIndexBuffer commands
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2015-12-11 16:54:44 -07:00
Brian Paul
71f19dd201 st/mesa: trivial indentation fix 2015-12-11 16:53:20 -07:00
Brian Paul
c877f1aeef util/blitter: minor formatting fixes 2015-12-11 16:53:20 -07:00
Jason Ekstrand
1c605c8dfa Merge remote-tracking branch 'mesa-public/master' into vulkan
This pulls in a shared local memory fix.
2015-12-11 14:29:13 -08:00
Jason Ekstrand
b8425bb1e8 i965/fs: Use the correct source for local memory load offsets
The offset for loads is in src[0].  This was a copy+paste error in the
nir_intrinsic_load/store refactoring.  This commit fixes a segfault in
ES31-CTS.compute_shader.work-group-size.  I have no idea how piglit failed
to catch this...

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93348
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-12-11 13:56:34 -08:00
Jason Ekstrand
d12ea21dd5 gen8/pipeline: Support vec4 vertex shaders
In order to actually get them, you need INTEL_DEBUG=vec4.
2015-12-11 13:25:17 -08:00
Kenneth Graunke
fadf378497 i965: Add Gen8+ tessellation control shader state (3DSTATE_HS).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-11 13:11:15 -08:00
Kenneth Graunke
b3c32f5f34 i965: Add Gen7+ tessellation engine state (3DSTATE_TE).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-11 13:11:15 -08:00