We can end up logging both the buffer that the toplevel cmdstream is
allocated, as well as the sub-allocated part of that buffer. Possibly
the kernel could do better about this, but to avoid undecodeable
cmdstream dumps and devcores, detect this case and deal with it.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20496>
We also want to ensure we don't hit the limit of max suballoc BOs.
Piglit drawoverhead would manage to hit this.
Fixes: 4861067689 ("freedreno/drm: Add sub-allocator")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20496>
Some CTS tests enable all extensions ... , which combined with having
no shader cache on some platforms results in some CTS tests timing
out (in particular tests recreating the device all the time).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20422>
Nothing significant in shader-db on RV530:
total instructions in shared programs: 134963 -> 134957 (<.01%)
instructions in affected programs: 1108 -> 1102 (-0.54%)
helped: 7
HURT: 1
total temps in shared programs: 17153 -> 17154 (<.01%)
temps in affected programs: 38 -> 39 (2.63%)
helped: 2
HURT: 3
Just some fluctuations from pair scheduling due to different code order.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20208>
There are still some ftruncs left as most of them originates in
nir_lower_int_to_float and that is currently called after nir_opt_algebraic
in ntt.
No change in shader-db.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20208>
Negligible amount of instructions saved on RV530:
total instructions in shared programs: 134970 -> 134963 (<.01%)
instructions in affected programs: 2273 -> 2266 (-0.31%)
helped: 9
HURT: 1
The one hurt shader is when we fail to recognize the x - ffract(x)
pattern and skip the don't emit ftrunc optimization as implemented
in the previous patch due to some non-trivial swizzles going on.
Signed-off-by: Pavel Ondračka <pave.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20208>
We already skip emitting ftrunc in nir_lower_int_to_float when there is
ffloor, fround or any other integer-making opcode preceding f2i32. However
if lower_ffloor is set for driver that doesn't support integers, the lowered
x - ffract(x) patterns would not be recognized and extra ftruct would be
emitted, doing unnecessary rounding.
This optimization only works if there is no non-trivial swizzling used for
the fadd, fneg and ffract involved, which seems to be 99% of the cases according
to my testing.
This is needed to enable nir ffloor lowering on r300 driver without regressions.
I'm not sure if this helps anybody else, the only hardware which sets
lower_ffloor and converts ints to floats (and can't do trunc) are some old
etnaviv cards, so maybe it will help there a bit.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20208>
I think we should distinguish between dynamic states (applications) and
hardware states, and this will allow us to use vk_viewport_state
instead of our own structs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20314>
dangling_attr_ref=true can be set when the following happens:
glBegin(GL_TRIANGLES)
glVertex(...)
glVertex(...)
glColor4(...)
glVertex(...)
When glColor4 is hit, the first 2 vertices are copied to the vertex_store
by upgrade_vertex, but since this is done before glColor4 new values are
copied, we make a note to fixup these attribute laters using dangling_attr_ref.
This causes very slow rendering. What this commit does instead, is in this
situation, the new attribute value are backported to the vertex store for the
copied vertices after upgrade_vertex is done updating the layout.
This avoids the slow corner case.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7912
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20495>
Given a GPU platform, there are multiple device ids. This commit
adds ability to specify device id for the shim, instead of using
one of the hard-coded device ids per platform.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20526>
Currently, process_singlesync_signals() checks if fd == -1 to handle
possible errors in the drmSyncobjExportSyncFile function. But, fd is not
initialized, which means that drmSyncobjExportSyncFile might fail and
the error will not be handled as fd might not be equal to -1.
Therefore, initialize the fd variable with value -1 to ensure proper
error handling.
cc: mesa-stable
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20475>
A new container registry was added recently in the fd.o infrastructure.
It is located in a datacenter that does not charge for bandwidth usage,
and aims to become the canonical registry in the future. It is however
currently configured to be a partial mirror of registry.fd.o, where
only the most-downloaded container images can be found.
The address of the new registry is specified in mesa/mesa's CI
variables, which means forks will default to registry.fd.o. However,
Valve Infra DUTs do not have access to the internet, and instead use
another cache proxy hosted locally on the CI gateways. This forced
Benjamin to overwrite the registry URL from harbor.freedesktop.org to
registry.freedesktop.org in 0bd9a062e1 ("CI: Overwrite valve infra's
registry").
After adding support for the new registry in valve infra, then
deploying the update, we are now able to make use of the new container
registry. This commit simply rewrites the URL harbor.freedesktop.org
into `{{ harbor_fdo_registry }}`. This variable is set in the valve
infra to point to the `host:ip` of the service, which means changes to
the way we deploy this service can be done on the valve-infra side
without needing to make changes to every project that makes use of our
machines.
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7913
Acked-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20450>
This is for VARYING_SLOT_VARx_16BIT slots varying streamout.
OpenGL ES will store 16bit medium precision varying to these slots.
Vulkan is not allowed to streamout varying less than 32bit.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20157>
It is combined with slot location to identify a varying
when using VARYING_SLOT_VARx_16BIT.
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20157>
The game uses texture2D() in glsl 4.40 shaders, but texture2D()
was moved to compat in 4.20.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20511>
For INTEL_MEASURE, ensure all prior instructions completed before
timestamp taken. Continue to support no CS flush case for Perfetto.
CS stall was dropped from pipecontrol when adding u_trace support.
Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20502>
For INTEL_MEASURE, ensure all prior instructions completed before
timestamp taken. Continue to support no CS flush case for Perfetto.
CS stall was dropped from pipecontrol when adding u_trace support.
Fixes: cc5843a573 ("anv: implement u_trace support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20502>
For now the restricted traces aren't available to the intel devs, so it
won't actually run for them, but I can manage that part for a bit until we
get the policy updated on the minio side (issue filed to do so).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20503>
This allows us to *much* more accurately express the app's barrier
requests. Unfortunately, there's still a few mismatches, so in those
cases we'll end up conservatively over-synchronizing/flushing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20324>
While enhanced barriers is a *much* closer model to Vulkan's, there's
still one big mismatch: Vulkan's "transfer" concept supports clears,
copies, and resolves, while D3D's closest match only supports copies.
So when doing clears and resolves, we need to transition from the copy
layout to the correct layout, and then back.
Internal barriers are done for some meta scenarios as well as render
pass initial layout transitions. These look more or less the same as
non-enhanced, we just want to avoid mixing the two paradigms if possible.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20324>
