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Author SHA1 Message Date
Timur Kristóf
348b8859dc ac/nir/tess: Only write tess factors that the TES reads. 
Otherwise we would write to a memory location reserved
for another per-patch output.

Fixes: 2cf7f282df
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11324
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29696>
 2024-06-18 12:06:21 +00:00
Alyssa Rosenzweig
15257b65c6 treewide: use nir_metadata_control_flow 
Via Coccinelle patch:

    @@
    @@

    -nir_metadata_block_index | nir_metadata_dominance
    +nir_metadata_control_flow

...plus some manual fixups for call sites missed by coccinelle.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Juan A. Suarez Romero <jasuarez@igalia.com> [broadcom]
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com> [lima]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29745>
 2024-06-17 16:28:14 -04:00
Daniel Schürmann
7af16e9f1e nir/shader_info: remove uses_demote 
This flag is mostly redundant with uses_discard and was only
introduced to implement demote with LLVM when it didn't have
that intrinsic.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>
 2024-06-17 19:37:16 +00:00
Daniel Schürmann
9b1a748b5e nir: remove nir_intrinsic_discard 
The semantics of discard differ between GLSL and HLSL and
their various implementations. Subsequently, numerous application
bugs occurred and SPV_EXT_demote_to_helper_invocation was written
in order to clarify the behavior. In NIR, we now have 3 different
intrinsics for 2 things, and while demote and terminate have clear
semantics, discard still doesn't and can mean either of the two.

This patch entirely removes nir_intrinsic_discard and
nir_intrinsic_discard_if and replaces all occurences either with
nir_intrinsic_terminate{_if} or nir_intrinsic_demote{_if} in the
case that the NIR option 'discard_is_demote' is being set.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>
 2024-06-17 19:37:16 +00:00
Daniel Schürmann
f3d8bd18dd nir: introduce discard_is_demote compiler option 
This new option indicates that the driver emits the same
code for nir_intrinsic_discard and nir_intrinsic_demote.
Otherwise, it is assumed that discard is implemented as
terminate.

spirv_to_nir uses this option in order to directly emit
nir_demote in case of OpKill.

RADV GFX11:
Totals from 3965 (4.99% of 79439) affected shaders:
MaxWaves: 119418 -> 119424 (+0.01%); split: +0.03%, -0.03%
Instrs: 1608753 -> 1620830 (+0.75%); split: -0.18%, +0.93%
CodeSize: 8759152 -> 8785152 (+0.30%); split: -0.18%, +0.48%
VGPRs: 152292 -> 149232 (-2.01%); split: -2.37%, +0.36%
Latency: 9162314 -> 10033923 (+9.51%); split: -0.46%, +9.97%
InvThroughput: 1491656 -> 1493408 (+0.12%); split: -0.10%, +0.22%
VClause: 21424 -> 21452 (+0.13%); split: -0.31%, +0.44%
SClause: 53598 -> 55871 (+4.24%); split: -2.15%, +6.39%
Copies: 90553 -> 90462 (-0.10%); split: -2.91%, +2.81%
Branches: 16283 -> 16311 (+0.17%)
PreSGPRs: 113993 -> 113254 (-0.65%); split: -1.84%, +1.19%
PreVGPRs: 110951 -> 108914 (-1.84%); split: -2.08%, +0.24%
VALU: 963192 -> 963167 (-0.00%); split: -0.01%, +0.01%
SALU: 87926 -> 90795 (+3.26%); split: -2.92%, +6.18%
VMEM: 25937 -> 25936 (-0.00%)
SMEM: 110012 -> 109799 (-0.19%); split: -0.20%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>
 2024-06-17 19:37:15 +00:00
Daniel Schürmann
d5821bdf7d radv: emit discard as demote by default 
Also removes radv_lower_discard_to_demote debug option.

Totals from 1506 (1.90% of 79439) affected shaders: (GFX11)
MaxWaves: 46432 -> 46448 (+0.03%)
Instrs: 664515 -> 667914 (+0.51%); split: -0.15%, +0.67%
CodeSize: 3569656 -> 3583440 (+0.39%); split: -0.12%, +0.51%
VGPRs: 50100 -> 49680 (-0.84%); split: -0.96%, +0.12%
Latency: 4221359 -> 4217875 (-0.08%); split: -0.67%, +0.59%
InvThroughput: 628809 -> 625565 (-0.52%); split: -0.53%, +0.02%
VClause: 9948 -> 9965 (+0.17%); split: -0.36%, +0.53%
SClause: 19656 -> 19695 (+0.20%); split: -0.77%, +0.97%
Copies: 32113 -> 33513 (+4.36%); split: -1.59%, +5.95%
Branches: 8406 -> 8378 (-0.33%)
PreSGPRs: 42328 -> 42555 (+0.54%); split: -0.39%, +0.93%
PreVGPRs: 38451 -> 38203 (-0.64%); split: -0.78%, +0.14%
VALU: 390770 -> 390208 (-0.14%); split: -0.16%, +0.02%
SALU: 43318 -> 46374 (+7.05%); split: -0.08%, +7.14%
VMEM: 15052 -> 15051 (-0.01%)
SMEM: 37225 -> 37215 (-0.03%); split: -0.03%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>
 2024-06-17 19:37:15 +00:00
Samuel Pitoiset
bd59478d2f radv: implement streamout on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29676>
 2024-06-17 14:46:36 +00:00
Samuel Pitoiset
aa9dfcad50 radv/nir: lower nir_intrinsic_load_xfb_state_address_gfx12_amd 
This intrinsic returns a 64-bit address that points to the streamout
state buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29676>
 2024-06-17 14:46:36 +00:00
Samuel Pitoiset
a9b8320031 radv: declare a new user SGPR for the streamout state buffer on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29676>
 2024-06-17 14:46:36 +00:00
Samuel Pitoiset
0e62c728eb ac/surface: add NBC view support on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29676>
 2024-06-17 14:46:36 +00:00
Samuel Pitoiset
ef6deb35ef radv: update configuring WALK_ALIGN8_PRIM_FITS_ST on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29676>
 2024-06-17 14:46:36 +00:00
Samuel Pitoiset
07eb970d67 radv: always save/restore all shader objects for internal operations 
If the application binds graphics shaders and that RADV performs an
internal operation with a compute pipeline, no shader objects would be
restored because binding the internal compute pipeline resets the ESO
state.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29678>
 2024-06-17 13:46:50 +00:00
Samuel Pitoiset
10bd300b68 radv: allow VK_NV_device_generated_commands_{compute} with LLVM 
DGC was disabled for LLVM due to 5/8 components SSBO stores but they
were not expected to work and this has been changed since a977a51a21
("radv: stop using 5/8 component SSBO stores"). No strong reason to
not enable it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29714>
 2024-06-17 12:02:10 +00:00
Samuel Pitoiset
8fcfadf28e radv: store a pointer to the logical device in dgc_cmdbuf 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29725>
 2024-06-17 06:45:44 +00:00
Samuel Pitoiset
7fb401c7b2 radv: add a helper to load the pipeline VA for DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29725>
 2024-06-17 06:45:44 +00:00
Samuel Pitoiset
57206eb888 radv: remove redundant nir_builder param in some DGC helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29725>
 2024-06-17 06:45:44 +00:00
Samuel Pitoiset
7ff6f492d5 radv: add new macros for emiting packets in DGC 
This is way cleaner.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29725>
 2024-06-17 06:45:44 +00:00
Samuel Pitoiset
85d79376d8 radv: do not use nir_pkt3() when the packet len is constant with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29725>
 2024-06-17 06:45:44 +00:00
Samuel Pitoiset
dd66e43bd9 radv: remove dynamic uniform/storage buffers support with DGC 
vkd3d-proton is the only user of NV DGC and it doesn't need that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29726>
 2024-06-17 06:13:57 +00:00
Daniel Schürmann
b7982152ff aco: use aco::monotonic_allocator for IDSet 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29713>
 2024-06-14 14:32:35 +00:00
Daniel Schürmann
97fd5d3f33 aco: make aco::monotonic_buffer_resource declaration visible for aco::IDSet 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29713>
 2024-06-14 14:32:35 +00:00
Daniel Schürmann
95967c2ca0 aco/reindex_ssa: replace live_var parameter with boolean 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29713>
 2024-06-14 14:32:35 +00:00
Daniel Schürmann
a497d105e3 aco: move live var information into struct Program 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29713>
 2024-06-14 14:32:35 +00:00
Daniel Schürmann
2322ab427e aco/scheduler: remove unused register_demand parameter 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29713>
 2024-06-14 14:32:35 +00:00
Pierre-Eric Pelloux-Prayer
5c50e028d1 ac/sqtt: make VA helpers static 
They're only used from ac_sqtt so don't expose them.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25397>
 2024-06-14 10:32:17 +02:00
Samuel Pitoiset
3f9fe2dbe1 radv: use BDA in the DGC prepare shader 
Only for buffers that are managed by the application (ie. preprocess,
stream and sequence buffers). For future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29605>
 2024-06-14 06:35:18 +00:00
Samuel Pitoiset
730ba8322f radv: fix incorrect buffer_list advance for multi-planar descriptors 
If we have an array of multi-planar descriptors, buffer_list was
incorrectly incremented and this could have overwritten some BO entries.

In practice, this situation should be very rare because most of the
applications enable the global BO list.

Cc: mesa-stable
Closes: #10559
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28816>
 2024-06-14 06:14:30 +00:00
Samuel Pitoiset
fa634503ce radv: emit SPI_GS_THROTTLE_CNTL1 when the attr ring is emitted 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29640>
 2024-06-13 10:24:11 +00:00
Samuel Pitoiset
028d573d37 radv: do not set registers set by CLEAR_STATE in the preamble on GFX10-11.5 
Based on RadeonSI 7baeb54c2a ("radeonsi: don't set registers set by
CLEAR_STATE in the preamble for gfx10-11").

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29640>
 2024-06-13 10:24:11 +00:00
Samuel Pitoiset
a95d7e46b6 radv: update VGT_TESS_DISTRIBUTION.ACCUM_ISOLINE value 
Based on PAL/RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29640>
 2024-06-13 10:24:11 +00:00
Daniel Schürmann
677c9d9e93 aco/assembler: fix GFX67 MTBUF opcode encoding 
Fixes: 56ac6f26e0 ('aco/assembler: slightly refactor MTBUF assembly for more readability')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29708>
 2024-06-13 09:18:05 +00:00
David Rosca
b754ad8f15 radv/video: Add missing VCN 3.0.2 to decoder init switch 
Fixes video decode on Steam Deck.

Fixes: d599391ac9 ("radv/video: use vcn ip version in more places.")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29688>
 2024-06-13 07:45:40 +00:00
Daniel Schürmann
56ac6f26e0 aco/assembler: slightly refactor MTBUF assembly for more readability 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29692>
 2024-06-12 11:41:58 +00:00
Daniel Schürmann
14f4906e53 aco/assembler: fix MTBUF opcode encoding on GFX11 
We have accidentally set the tfe bit for some opcodes.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29692>
 2024-06-12 11:41:58 +00:00
Leo Liu
448c716358 ac/surface/tests: add the test for ADDR3_256B_2D 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29541>
 2024-06-11 12:29:11 -04:00
Leo Liu
59e813d953 ac/surface: add GFX12 256B tile mode for video 
With VCN5, the DPB buffer uses gfx12 tile/swizzle mode.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29541>
 2024-06-11 12:29:11 -04:00
Rhys Perry
7a4f121c5d aco: remove some missing label resets 
In the case of:
   c = xor(a, b)
   d = not(c)
   xor(d, e)
it will be optimized to:
   d = xnor(a, b)
   xor(d, e)
because "d" would still had a label with "instr=not(c)", it would then be
further optimized to:
   d = xnor(a, b)
   xnor(c, e)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11309
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29650>
 2024-06-11 09:30:16 +00:00
Samuel Pitoiset
51d1e005e8 radv: use the common SQTT implementation 
I have verified the generated command stream using PM4 is similar to
the previous one on POLARIS10, VEGA10, NAVI21 and NAVI31.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
ea8f29b4a7 radv: emit more consecutive registers for SQTT on GFX8-9 
This change is only useful to compare the command stream generated by
PM4 in the next commit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
a373ba92c3 amd: add a common implementation for SQTT using PM4 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
2fab42ad2e amd: mark more registers that need RESET_FILTER_CAM in PM4 
For SQTT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
0c08673656 amd: allow to emit privileged config registers in PM4 
For SQTT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
b82e5c8da8 ac,radv,radeonsi: add more parameters to ac_sqtt 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
155399d03b ac,radv: add a helper for SQTT control register 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Pierre-Eric Pelloux-Prayer
a7880f3edb radv/sqtt: use radeon_check_space before emit_spm_* 
This fixes the following error on a rdna2:

   radeon_set_uconfig_reg_seq: Assertion `cs->cdw + 2 + num <= cs->reserved_dw' failed.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00
Samuel Pitoiset
a80a1c9838 radv: don't assume that TC_ACTION_ENA invalidates L1 cache on gfx9 
Ported from RadeonSI 279315fd73 ("radeonsi: don't assume that
TC_ACTION_ENA invalidates L1 cache on gfx9")

Thanks to Rhys for noticing this by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29644>
 2024-06-11 06:15:12 +00:00
Friedrich Vock
15f2c9c553 aco: Limit rt stages to 128 vgprs 
Totals from 35472 (7.40% of 479373) affected shaders:

MaxWaves: 206239 -> 283776 (+37.60%)
Instrs: 193922210 -> 202721106 (+4.54%)
CodeSize: 1056819972 -> 1110833680 (+5.11%); split: -0.00%, +5.11%
VGPRs: 6026704 -> 4540416 (-24.66%)
SpillSGPRs: 23742 -> 25754 (+8.47%)
SpillVGPRs: 118897 -> 2295118 (+1830.34%)
Scratch: 7201792 -> 152752128 (+2021.03%)
Latency: 2713432565 -> 3194796286 (+17.74%); split: -0.20%, +17.94%
InvThroughput: 1052131232 -> 935049835 (-11.13%); split: -16.59%, +5.46%
VClause: 6972784 -> 8716721 (+25.01%); split: -0.02%, +25.03%
SClause: 4879313 -> 4852452 (-0.55%); split: -0.88%, +0.33%
Copies: 32782141 -> 35223995 (+7.45%)
Branches: 11075847 -> 11094087 (+0.16%); split: -0.00%, +0.17%
VALU: 118525960 -> 120929058 (+2.03%)
SALU: 33924572 -> 33973293 (+0.14%); split: -0.03%, +0.17%
VMEM: 12419116 -> 17104582 (+37.73%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29593>
 2024-06-10 19:39:52 +00:00
Friedrich Vock
ec8512ce85 aco/spill: Don't spill phis with all-undef operands 
Fixes some crashes when limiting RT stages to 128 VGPRs.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29593>
 2024-06-10 19:39:52 +00:00
Samuel Pitoiset
128cca21c0 radv: pass a radv_shader to radv_get_compute_pipeline_metadata() 
And rename to radv_get_compute_shader_metadata().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29652>
 2024-06-10 17:31:12 +00:00
Ruijing Dong
8cd53d95fe radesonsi/vcn: update vcn4 tile processing logic 
Vcn4 tile number calculation doesn't consider
some input case, which could result in output
bitstream corruption, this fixed the issue.

Not using the number_of_tiles directly but from
calculation. Also change to re-use some macros
from local vcn_5_0.c to ac_vcn_enc.h header file.

Updated vcn4 spec_misc_av1 ip package.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29556>
 2024-06-10 13:12:20 +00:00