Commit graph

24018 commits

Author SHA1 Message Date
Maciej Cencora
3445f47697 r300g: VBOs WIP 2009-11-07 11:53:13 -08:00
Maciej Cencora
d8592d1724 r300g: add missing flush 2009-11-07 11:53:13 -08:00
Maciej Cencora
c7dfffc5d5 r300g: enable CS dumping 2009-11-07 11:53:13 -08:00
Maciej Cencora
6acb26eadf r300g: move vborender context function to seperate file
r300g: Un-migrate r300_draw_render.

It'll make maintaining the SW TCL path easier.
2009-11-07 11:53:06 -08:00
brian
18768393d1 mesa: move code after decl
Fixes bug 24967.
2009-11-07 08:18:07 -07:00
Christoph Bumiller
44cb5b5c66 nv50: enable all 32 threads of a warp
This should be the default setting.
See also 7d967b9b7c.
2009-11-07 10:48:36 +01:00
Eric Anholt
8baee3d25b i965: Use Compr4 instruction compression mode on G4X and newer.
No statistically significant performance difference at n=3 with either
openarena or my GL demo, but cutting program size seems like a good
thing to be doing for the hypothetical app that has a working set near
icache size.
2009-11-06 21:24:22 -08:00
Eric Anholt
ec66644ed0 i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c 2009-11-06 21:08:55 -08:00
Eric Anholt
cfa927766a i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c
This should fix issues with antialiased lines in GLSL.
2009-11-06 21:08:55 -08:00
Eric Anholt
2b58c31257 i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's
had been improved, and pixel_w should no longer stomp on a neighbor to dst.
2009-11-06 21:08:55 -08:00
Eric Anholt
1e5400c575 i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c. 2009-11-06 21:08:54 -08:00
Eric Anholt
7059aa0eff i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c. 2009-11-06 21:08:54 -08:00
Eric Anholt
726ad15606 i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c 2009-11-06 21:08:54 -08:00
Eric Anholt
bad5b120be i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c 2009-11-06 21:08:54 -08:00
Eric Anholt
06c1bc8a22 i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code. 2009-11-06 21:08:54 -08:00
Eric Anholt
90629704ef i965: Use a normal alu1 emit for OPCODE_TRUNC. 2009-11-06 21:08:54 -08:00
Eric Anholt
71af508072 i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c
This drops support for get_src_reg_imm in these, but the prospect of getting
brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
2009-11-06 21:08:54 -08:00
Eric Anholt
0f34cdf621 i965: Collect GLSL src/dst regs up in generic code.
This matches brw_wm_emit.c, which we'll be using shortly.  There's a
possible penalty here in that we'll allocate registers for unused channels,
since we aren't doing ref tracking like brw_wm_pass*.c does.  However, my
measurements on GM965 don't show any for either OA or UT2004 with the GLSL
path forced.
2009-11-06 21:08:54 -08:00
Zack Rusin
e521bf7706 st/xorg: implement batching for the composite op
something is broken so disabled for now
2009-11-06 22:08:21 -05:00
Zack Rusin
4322346f3f st/xorg: batch solid fill requests
instead of lots of very small transfers, one larger is a lot better
for performance
2009-11-06 22:08:21 -05:00
Zack Rusin
e1730632aa st/xorg: start accumulating vertices in a common buffer 2009-11-06 22:08:21 -05:00
Zack Rusin
3f7df23ff5 st/xorg: use quads instead of triangle fans
easier to split, accumulate and batch those
2009-11-06 22:08:21 -05:00
Zack Rusin
6c44d399bd st/xorg: make the buffer size global 2009-11-06 22:08:21 -05:00
Eric Anholt
6b0bcfafab mesa: Reduce the source channels considered in optimization passes.
Depending on the writemask or the opcode, we can often trim the source
channels considered used for dead code elimination.  This saves actual
instructions on 965 in the non-GLSL path for glean glsl1, and cleans up
the writemasks of programs even further.
2009-11-06 14:27:35 -08:00
Eric Anholt
f3cacfe216 mesa: Fix remove_instructions to successfully remove when removeFlags[0].
This fixes the dead code elimination to work on the particular code
mentioned in the previous commit.
2009-11-06 13:16:49 -08:00
Eric Anholt
e4e312d493 mesa: Add an optimization path to remove use of pointless MOVs.
GLSL code such as:
	vec4 result = {0, 1, 0, 0};
	gl_FragColor = result;

emits code like:
  0: MOV TEMP[0], CONST[0];
  1: MOV OUTPUT[1], TEMP[0];

and this replaces it with:
  0: MOV TEMP[0], CONST[0];
  1: MOV OUTPUT[1], CONST[0];

Even when the dead code eliminator fails to clean up a now-useless MOV
instruction (since it doesn't do live/dead ranges), this should at reduce
dependencies.
2009-11-06 13:16:49 -08:00
Eric Anholt
ee0a9e6e10 mesa: Fix up the remove_dead_code pass to operate on a channel basis.
This cleans up a bunch of instructions in GLSL programs to have limited
writemasks, which would translate to wins in shaders that hit the i965
brw_wm_glsl.c path by depending less on in-driver optimizations.  It will
also help hit other optimization passes I'm looking at.
2009-11-06 13:16:49 -08:00
Brian Paul
3105f3aa88 intel: better front color buffer test in intelClear() 2009-11-06 13:52:48 -07:00
Eric Anholt
8395da2e8a i965: Always pass the size argument to brw_cache_data.
This keeps the individual state files from having to export their
structures for brw_state_cache initialization.
2009-11-06 11:37:32 -08:00
Eric Anholt
1166294d1d intel: Finish removing the fallback code for bug #16697.
I fixed it properly as of 7216679c19.
2009-11-06 11:37:32 -08:00
Eric Anholt
75bdbdd90b intel: Don't validate in a texture image used as a render target.
Otherwise, we could lose track of rendering to that image, which could
easily happen during mipmap generation.
2009-11-06 11:37:32 -08:00
Eric Anholt
6b68482e68 mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture()
This is probably not 100% complete (bind vs unbind may still not pair up
exactly), but it should help out drivers which are relying on
FinishRenderTexture to be called when we're done rendering to a particular
texture level, not just when we're done rendering to the object at all.
This is the case for the one consumer of FinishRenderTexture() so far: the
gallium state tracker.  Noticed when trying to make use of FRT() in the intel
driver.
2009-11-06 11:37:32 -08:00
Eric Anholt
8df81bca17 intel: Clean up some extra struct indirection in finalize. 2009-11-06 11:37:32 -08:00
Eric Anholt
ee7dfbbd6c intel: Use _mesa_get_current_tex_object() to clean up TFP path. 2009-11-06 11:37:31 -08:00
Eric Anholt
8f30ceaaef intel: Remove duplicated arguments from intel_miptree_match_image(). 2009-11-06 11:37:31 -08:00
Eric Anholt
2bc8bcdcd3 i965: Remove an XXX comment for testing some code that seems to work. 2009-11-06 11:37:31 -08:00
Eric Anholt
bb2dd50be0 intel: Remove obsolete comment about GEM in the spans code. 2009-11-06 11:37:31 -08:00
Eric Anholt
8e0f40d287 intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.
This should do all the things that MI_FLUSH did, but it can be pipelined
so that further rendering isn't blocked on the flush completion unless
necessary.
2009-11-06 11:37:31 -08:00
Eric Anholt
caf3038123 Make a convenient int for what chipset generation we're on.
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc",
and compares on generation are often easier than stringing together a bunch
of chipset checks.
2009-11-06 11:37:31 -08:00
Ian Romanick
4e4c2ee1fd Merge branch 'mesa_7_6_branch'
This should fix the memory leaks in the assembly parser without the
regressions.

The conflicts in program_lexer.l were related to changes in returning
strings between the branches (always return IDENTIFIER vs. returing
either IDENTIFIER or USED_IDENTIFIER).

The conflicts in program_parse.y were related to two changes in master
One change prints a variable name in an error message.  The other
change adds outputVarSize to the OUTPUT_statement rule.  The cause the
position of the IDENTIFIER to change from $2 to $3.

Conflicts:
	src/mesa/shader/lex.yy.c
	src/mesa/shader/program_lexer.l
	src/mesa/shader/program_parse.tab.c
	src/mesa/shader/program_parse.y
2009-11-06 11:17:00 -08:00
Ian Romanick
9348ac03ce ARB prog parser: Regenerate parser from previous commits. 2009-11-06 10:46:23 -08:00
Ian Romanick
d8e256f923 ARB prog parser: Release old program string in _mesa_parse_arb_{fragment,vertex}_program
The program structure passed to _mesa_parse_arb_program is just a
place holder.  The stings that actually need to be released are only
known to the functions calling _mesa_parse_arb_program, so they should
be freed there.
2009-11-06 10:46:22 -08:00
Ian Romanick
301a9b7e28 ARB prog parser: Release strings returned from the lexer that don't need to be kept 2009-11-06 10:46:22 -08:00
Ian Romanick
1c7337d46e Revert "ARB prog parser: Fix epic memory leak in lexer / parser interface"
This reverts commit 93dae6761b.

This change was completely broken when the parser uses multiple
strings in a single production.  It would be nice if bug fixes could
initially land somewhere other than the stable branch.
2009-11-06 10:46:22 -08:00
José Fonseca
96e938f62c llvmpipe: Fix build with llvm 2.6.
Fixes bug 24949.
2009-11-06 15:08:05 +00:00
Brian Paul
38d3c156dc intel: call intel_check_front_buffer_rendering() in intelClear()
fixes bug 24953.
2009-11-06 08:00:38 -07:00
José Fonseca
577a598dc9 mesa: Export S3_s3tc as well.
Used in Quake3.
2009-11-06 12:06:45 +00:00
José Fonseca
f611425101 mesa: Translate MAP_UNSYNCHRONIZED_BIT. 2009-11-06 12:06:44 +00:00
José Fonseca
244591ae7b gallium: Add UNSYNCHRONIZED cpu access flag. Document others. 2009-11-06 12:06:44 +00:00
Zack Rusin
25728860fc st/xorg: unify vertex buffer handling
first step on our way to batching
2009-11-06 00:19:54 -05:00