Commit graph

28654 commits

Author SHA1 Message Date
Kenneth Graunke
32630e211e nir: Report progress from nir_lower_alu_to_scalar.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-09-14 12:01:49 -07:00
Martina Kollarova
2527e18eeb gallium: fix return value check
A possible error (-1) was being lost because it was first converted to an
unsigned int and only then checked.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Martina Kollarova <martina.kollarova@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2016-09-14 14:36:43 +01:00
Marek Olšák
ab29788250 radeonsi: reload PS inputs with direct indexing at each use (v2)
The LLVM compiler can CSE interp intrinsics thanks to
LLVMReadNoneAttribute.

26011 shaders in 14651 tests
Totals:
SGPRS: 1146340 -> 1132676 (-1.19 %)
VGPRS: 727371 -> 711730 (-2.15 %)
Spilled SGPRs: 2218 -> 2078 (-6.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size: 35841268 -> 36009732 (0.47 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 222559 -> 224779 (1.00 %)
Wait states: 0 -> 0 (0.00 %)

v2: don't call load_input for fragment shaders in emit_declaration

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-14 12:33:00 +02:00
Marek Olšák
007b512f9d radeonsi: get rid of constant buffer preloading
26011 shaders in 14651 tests
Totals:
SGPRS: 1152636 -> 1146340 (-0.55 %)
VGPRS: 728198 -> 727371 (-0.11 %)
Spilled SGPRs: 3776 -> 2218 (-41.26 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size: 35835152 -> 35841268 (0.02 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 222372 -> 222559 (0.08 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-09-14 12:32:59 +02:00
Marek Olšák
16be87c904 radeonsi: get rid of img/buf/sampler descriptor preloading (v2)
26011 shaders in 14651 tests
Totals:
SGPRS: 1251920 -> 1152636 (-7.93 %)
VGPRS: 728421 -> 728198 (-0.03 %)
Spilled SGPRs: 16644 -> 3776 (-77.31 %)
Spilled VGPRs: 369 -> 369 (0.00 %)
Scratch VGPRs: 1344 -> 1344 (0.00 %) dwords per thread
Code Size: 36001064 -> 35835152 (-0.46 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 222221 -> 222372 (0.07 %)
Wait states: 0 -> 0 (0.00 %)

v2: merge codepaths where possible

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-14 12:32:59 +02:00
Marek Olšák
22797d7d83 radeonsi: rename get_sampler_desc -> load_sampler_desc
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-09-14 12:32:59 +02:00
Marek Olšák
5f0a8fbcc8 radeonsi: cosmetic changes in si_shader.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-09-14 12:32:59 +02:00
Marek Olšák
afaf27bff3 radeonsi: load streamout buffer descriptors before use (v2)
v2: inline the code and remove the conditional that's a no-op now

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-14 12:32:59 +02:00
Eric Anholt
f597ac3966 vc4: Implement job shuffling
Track rendering to each FBO independently and flush rendering only when
necessary.  This lets us avoid the overhead of storing and loading the
frame when an application momentarily switches to rendering to some other
texture in order to continue rendering the main scene.

Improves glmark -b desktop:effect=shadow:windows=4 by 27%
Improves glmark -b
    desktop:blur-radius=5:effect=blur:passes=1:separable=true:windows=4
    by 17%

While I haven't tested other apps, this should help X rendering a lot, and
I've heard GLBenchmark needed it too.
2016-09-14 06:25:41 +01:00
Eric Anholt
f473348468 vc4: Handle resolve skipping at job submit time.
This is done in vc4_flush currently, but I'm going to make the job always
track the surfaces it might be rendering to instead of putting in the
destinations at flush time.
2016-09-14 06:08:03 +01:00
Eric Anholt
9688166bd9 vc4: Move the render job state into a separate structure.
This is a preparation step for having multiple jobs being queued up at the
same time.
2016-09-14 06:08:03 +01:00
Eric Anholt
c31a7f529f vc4: Always unref the current job surfaces at job reset time.
Drops some tricky logic in vc4_flush() trying to update the pointers, and
fixes a broken lack of unref for MSAA surfaces at context destroy time.
2016-09-14 06:08:03 +01:00
Eric Anholt
774a556b6d vc4: Move job-submit skip cases to vc4_job_submit().
For calling job_submit() directly, I need the skipping here.
2016-09-14 06:08:03 +01:00
Eric Anholt
0ef1b32ebb vc4: Move bin CL trailer to job_submit() time.
To implement job shuffling, I want to be able to call submit() on specific
jobs, turning vc4_flush() into the context's flush-all-jobs hook.
2016-09-14 06:08:03 +01:00
Eric Anholt
a2014c2eb9 vc4: Simplify the DISCARD_RANGE handling
It's really just an upgrade to attempting WHOLE_RESOURCE.  Pulling the
logic out caught two bugs in it: We would try to do so on cubemaps (even
though we're only mapping 1 of the 6 slices), and we would break
persistent coherent mappings by trying to reallocate when we shouldn't.
2016-09-14 06:08:03 +01:00
Eric Anholt
21a27ad956 vc4: Fix incorrect clearing of Z/stencil when cleared separately.
The clear of Z or stencil will end up clearing the other as well, instead
of masking.  There's no way around this that I know of, so if we are
clearing just one then we need to draw a quad.

Fixes a regression in the job-shuffling code, where the clear values move
to the job and don't just have the last clear's value laying around when
you do glClear(DEPTH) and then glClear(STENCIL) separately
(ext_framebuffer_multisample-clear 4 depth)).

This causes regressions in ext_framebuffer_multisample/multisample-blit
depth and ext_framebuffer_multisample/no-color depth, but these were
formerly false positives due to the reference image also being black.  Now
the reference and test images are both being drawn, and it looks like
there's an incorrect resolve of depth during blitting to an MSAA FBO.
2016-09-14 06:08:03 +01:00
Marek Olšák
524fd55d2d tgsi/scan: don't set interp flags for inputs only used by INTERP instructions
radeonsi depends on the interp flags a little bit too much.

This fixes 9 randomly failing tests:
  GL45-CTS.shader_multisample_interpolation.render.interpolate_at_centroid.*

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
15a127bc2c radeonsi: fix FP64 UBO loads with indirect uniform block indexing
No known tests.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
35d284d08e winsys/amdgpu: don't assume GTT if the VRAM flag isn't set
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
6df872df59 radeonsi: clean up CP DMA emit code
Unify the clear and copy paths, clean up the definitions.
It looks more like a rework. It's a preparation for GDS support,
which might or might not come.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
84860dd0bb radeonsi: print the IB and buffer list in VM fault reports
This is a fallout from reworking the debug flags.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
fd69fa65a8 radeonsi: add sampler view BOs to the BO list last
If si_sampler_view_add_buffer ends up flushing, then the code
in begin_new_cs would previously have added the buffer(s) for
whatever was previously bound to that slot. Now it would add only
the new buffer.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
275c073c6a radeonsi: export SampleMask from pixel shaders at full rate
Heaven and Valley write gl_SampleMask and not Z.
Use 16_ABGR instead of 32_ABGR if Z isn't written.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
b89854b0c7 gallium/radeon: set new r600_resource fields correctly in other places too
This was missed in:

    commit 0d2e43fcb1
    Author: Marek Olšák <marek.olsak@amd.com>
    Date:   Thu Aug 18 16:30:00 2016 +0200

        gallium/radeon: derive buffer placement and flags only at initialization

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
c723acc03d ddebug: dump shader buffers and images
this was unimplemented

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Marek Olšák
fdd457c89f ddebug: fix a crash in resource_get_handle
broken recently

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-13 20:38:25 +02:00
Jan Vesely
b671909d27 radeon: Don't check DCC on pipe buffers
Fixes segfaults in EG compute since:
commit 21de3be8e6
radeonsi: fix texture format reinterpretation with DCC

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-13 14:23:26 -04:00
Andy Furniss
304f70536a vl/util: Fix YV12/I420 convert to NV12 U/V reversal
Fix VAAPI YV12/I420 convert to NV12 U/V reversal.
Input order is YVU when this is called.

Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
2016-09-13 13:58:40 -04:00
Mauro Rossi
6b9d7e69ee android: add support for libmesa_amdgpu_addrlib
Android porting of the following commits:

f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place."
69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code"

This patch fixes android building errors

Reviewed-by: Dave Airlie <airlied@redhat.com>
2016-09-13 10:06:04 +10:00
Julien Isorce
bf901a2f8c st/va: also honors interlaced preference when providing a video format
This fixes a crash when using the prefered video format with vaapisink
on Nvidia hardwares.
Also caught by the following assert:
  nouveau_vp3_video.c:91: Assertion `templat->interlaced' failed.

TEST= gst-launch-1.0 videotestsrc ! video/x-raw, format=NV12 ! vaapisink

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Víctor Manuel Jáquez Leal <vjaquez@igalia.com>
Tested-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-12 22:17:40 +01:00
Samuel Pitoiset
3f3640c86c tgsi: document semantics for compute shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-12 22:15:10 +02:00
Marek Olšák
546bc07349 radeonsi: don't preload constants at the beginning of shaders
LLVM can CSE the loads, thus we can always re-load constants before each
use. The decrease in SGPR spilling is huge.

The best improvements are the dumbest ones.

26011 shaders in 14651 tests
Totals:
SGPRS: 1453346 -> 1251920 (-13.86 %)
VGPRS: 742576 -> 728421 (-1.91 %)
Spilled SGPRs: 52298 -> 16644 (-68.17 %)
Spilled VGPRs: 397 -> 369 (-7.05 %)
Scratch VGPRs: 1372 -> 1344 (-2.04 %) dwords per thread
Code Size: 36136488 -> 36001064 (-0.37 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 219315 -> 222221 (1.33 %)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-12 21:06:57 +02:00
Boyuan Zhang
e5009b7c26 st/va: enable vbr rate control for vaapi encode
This patch enables variable bit-rate for vaapi encoding. According to va.h,
target bit-rate equals to maximum bit-rate multiplies by target_percentage.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-12 10:34:53 -04:00
Leo Liu
6a7f79af9b vl/rbsp: match initial escaped bits with valid in the buffer
Otherwise the check for the three byte will not make sense.

Signed-off-by: Leo Liu <leo.liu@amd.com>
2016-09-12 10:09:27 -04:00
Nicolai Hähnle
b8703e363c winsys/radeon: rename nrelocs, crelocs to max_relocs, num_relocs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:55 +02:00
Nicolai Hähnle
d66bbfbede winsys/radeon: don't pre-allocate the relocations array
It's really not necessary. Switch to an exponential resizing strategy.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:53 +02:00
Nicolai Hähnle
f47da2e34f winsys/radeon: remove unused radeon_cs_context::priority_usage
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:51 +02:00
Nicolai Hähnle
17fff0c2de winsys/amdgpu: remove amdgpu_cs_lookup_buffer
The radeonsi driver doesn't and shouldn't care about the buffer index.
Only the virtual addresses matter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:47 +02:00
Nicolai Hähnle
12657a7abf winsys/amdgpu: remove unused field domains from amdgpu_cs_buffer
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:07 +02:00
Nicolai Hähnle
3cdeb2a177 winsys/amdgpu: remove initial buffer list allocation
It's really not necessary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:04 +02:00
Nicolai Hähnle
cc53dfda9f winsys/amdgpu: extract adding a new buffer list entry into its own function
While at it, try to be a little more robust in the face of memory allocation
failure.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:55:01 +02:00
Nicolai Hähnle
11cbf4d7ae winsys/amdgpu: use only one fence per BO
The fence that is added to the BO during flush is guaranteed to be
signaled after all the fences that were in the fences array of the BO
before the flush, because those fences are added as dependencies for the
submission (and all this happens atomically under the bo_fence_lock).

Therefore, keeping only the last fence around is sufficient.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:54:59 +02:00
Nicolai Hähnle
480ac143df winsys/amdgpu: add do_winsys_deinit function
The idea is to have matching init/deinit functions so that deinit can be
re-used for cleanup in the error path of amdgpu_winsys_create.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:54:56 +02:00
Nicolai Hähnle
9fb8d354ca winsys/amdgpu: clean up error paths in amdgpu_winsys_create
No need to call pb_cache_deinit, because the cache hasn't been initialized
at that point.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:54:53 +02:00
Nicolai Hähnle
a6c38d47d4 gallium/radeon: page alignment for buffers is unnecessary
In some places (e.g. shader program pointers) we require 256 bytes alignment.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:54:45 +02:00
Nicolai Hähnle
339867c077 gallium/radeon/winsyses: remove #includes of pb_bufmgr.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-12 13:54:36 +02:00
Ilia Mirkin
148fbf32a8 freedreno/a3xx: disable filtering for texture buffers and int textures
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-11 13:14:06 -04:00
Niels Ole Salscheider
cfa914a1b4 st/clover: Define __OPENCL_VERSION__ on the device side
This is required by the OpenCL standard.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2016-09-10 15:48:54 -07:00
Ilia Mirkin
a8c0c7301c gm107/ir: allow indirect inputs to be loaded by frag shader
Looks like the GM107 IPA op does not allow a separate offset when
using an indirect register. Instead we must use AL2P like we do for
indirect vertex operations on Kepler+.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-09-10 13:40:04 -04:00
Ilia Mirkin
a22aee5ad1 gm107/ir: AL2P writes to a predicate register
We have to force it to write to predicate 7 (aka PT) in order for it not
to mess up another predicate. Unclear what would be returned in the
predicate, perhaps an error code for out-of-bounds requests. Blob
doesn't seem to check it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2016-09-10 13:36:20 -04:00