Commit graph

85534 commits

Author SHA1 Message Date
Samuel Pitoiset
304de4edb9 mesa: add KHR_no_error support for glGetImageHandleARB()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:21:04 +02:00
Samuel Pitoiset
530ff887eb mesa: add KHR_no_error support for glGetTexture*HandleARB()
It would be nice to have a no_error path for
_mesa_test_texobj_completeness() because this function doesn't
only test if the texture is complete.

Anyway, that seems enough for now and a bunch of checks are
skipped with this patch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:21:01 +02:00
Samuel Pitoiset
0fb2c89c71 mesa: add KHR_no_error support for glMake{Image,Texture}Handle*ResidentARB()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:20:59 +02:00
Samuel Pitoiset
d7bee4a022 mesa: add KHR_no_error support for glIs{Image,Texture}HandleResidentARB()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:20:57 +02:00
Samuel Pitoiset
6ff6863c32 radeonsi: reduce overhead for resident textures which need color decompression
This is done by introducing a separate list.

si_decompress_textures() is now 5x faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:38 +02:00
Samuel Pitoiset
06ed251c32 radeonsi: reduce overhead for resident textures which need depth decompression
This is done by introducing a separate list.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:36 +02:00
Samuel Pitoiset
705a6a560e radeonsi: use util_dynarray_foreach for bindless resources
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:34 +02:00
Samuel Pitoiset
db73595018 mesa/util: add util_dynarray_clear() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:32 +02:00
Samuel Pitoiset
8d9e76ce1f gallium/radeon: add a new HUD query for the number of resident handles
Useful for debugging performance issues when ARB_bindless_texture
is enabled. This query doesn't make a distinction between texture
and image handles.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:08:08 +02:00
Topi Pohjolainen
e08171ef53 i965/gen4: Refactor depth/stencil rebase
Effectively there is the same code twice, once for depth and
again for stencil.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
84b195b361 i965: Drop depth/stencil miptree pointers in alignment workaround
In brw_workaround_depthstencil_alignment() corresponding
renderbuffers are always set to refer to the same temp miptrees.
There is no need to carry them in context.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
cd0804c359 i965/gen4: Simplify depth/stencil invalidate check
There is no separate stencil on gen < 6.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
bb5d3fe96a i965/gen4: Remove redundant check for depth when rebasing stencil
In case of gen < 6 stencil (if present) is always combined with
depth. Both stencil and depth attachments point to the same
physical surface.
Alignment workaround starts by considering depth and updates
stencil accordingly. Current logic continues with stencil and
in vain considers the case where depth would refer to different
surface than stencil.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
04524ac0d4 i965/gen4: Remove non-existing stencil and hiz buffer setup
Separate stencil and hiz are only enabled for gen6+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Mauro Rossi
58d337941e android: ac: add missing libdrm_amdgpu shared dependency
Fixes building errors in amd/common:

target  C: libmesa_amd_common <= external/mesa/src/amd/common/ac_gpu_info.c
...
target  C: libmesa_amd_common <= external/mesa/src/amd/common/ac_surface.c
...

external/mesa/src/amd/common/ac_gpu_info.h:31:10: fatal error: 'amdgpu.h' file not found
         ^
2 errors

Fixes: 98a2492 ("ac_surface: use radeon_info from ac_gpu_info")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-06-17 18:38:31 +01:00
Emil Velikov
68aa39d5c2 r600: include libelf headers only as needed
Headers are required only when building with OpenCL. As we're building
w/o it libelf may be missing, hence we'll error out as below:

src/gallium/drivers/r600/evergreen_compute.c:27:10:
fatal error: 'gelf.h' file not found
         ^
1 error generated.

Fixes: d96a210842 ("r600g,compute: provide local copy of functions from
ac_binary.c")
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-17 16:57:18 +01:00
Emil Velikov
1f958c1337 radeonsi: include ac_binary.h for struct ac_shader_binary
The header embeds the struct so it needs the header inclusion instead of
the dummy forward declaration.

Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Tom Stellard <tstellar@redhat.com>
Fixes: 32206c5e56 ("radeonsi: Add radeon_shader_binary member to struct
si_shader")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-17 11:38:02 +01:00
Emil Velikov
7e1c42cf89 r600, radeon: move radeon_shader_binary_{init,clean} back to radeon
Those are used by r600 and radeonsi, so moving them within the former
was a bad idea.

Fixes: d96a210842 ("r600g,compute: provide local copy of functions
from ac_binary.c")
Cc: Jan Vesely <jan.vesely@rutgers.edu>
Cc: Aaron Watry <awatry@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-17 11:37:58 +01:00
Emil Velikov
84bf7e5ad6 ac: resolve conflicts introduced with "ac: remove amdgpu.h dependency"
The commit did not add the relevant includes - in particular
stdint.h and stdbool.h for the respective standard types.

At the same time, the amdgpu_device_handle typedef redeclaration was
off.

Fixes: 81945ded0d ("ac: remove amdgpu.h dependency")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101471
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Gregor Münch <gr.muench@gmail.com>
Reported-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reported-by: Gregor Münch <gr.muench@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-17 11:37:51 +01:00
Topi Pohjolainen
6967285981 i965/gen4: Set depth offset when there is stencil attachment only
Current version fails to set depthstencil.depth_offset when there
is only stencil attachment (it does set the intra tile offsets
though). Fixes piglits:

g45,g965,ilk:   depthstencil-render-miplevels 1024 s=z24_s8
g45,ilk:        depthstencil-render-miplevels 273 s=z24_s8

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-17 06:38:56 +03:00
Topi Pohjolainen
a8e89cd539 i965/gen6: Remove dead code in hiz surface setup
In intel_hiz_miptree_buf_create() the miptree is unconditionally
created with MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-17 06:38:56 +03:00
Topi Pohjolainen
0d1af164e1 intel/isl/gen6: Allow arrayed stencil
Nothing prevents arrayed stencil surfaces even though hardware
doesn't support mipmapping.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-17 06:38:56 +03:00
Brian Paul
e3f5b8ac16 svga: add new num-failed-allocations HUD query
This counter is incremented if we fail to allocate memory for
vertex/index/const buffers, textures, etc.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-06-16 17:04:08 -06:00
Brian Paul
b27281c110 gallium/hud: support GALLIUM_HUD_DUMP_DIR feature on Windows
Use a dummy implementation of the access() function.  Use \ path separator.
Add a few comments.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-06-16 17:04:02 -06:00
Brian Paul
d6cb912d65 svga: add a few minor comments
Trivial.
2017-06-16 17:03:01 -06:00
Brian Paul
15f4c3ada4 mesa: whitespace fixes in enable.c
Remove trailing whitespace, replace tabs w/ spaces, etc.  Trivial.
2017-06-16 17:03:01 -06:00
Rafael Antognolli
c2b5a26dc2 i965: Convert SF_STATE to genxml.
This patch finishes the work done by Ken of converting SF_STATE to genxml, and
merges it with gen6+ code for emitting that state.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16 15:01:16 -07:00
Rafael Antognolli
3a767f8b06 genxml: The viewport state offset is actually an address.
This fixes code generation on gen45.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16 15:01:16 -07:00
Rafael Antognolli
ad109c16c2 genxml: Rename fields to match gen6+.
"Anti-aliasing Enable" to "Anti-Aliasing Enable".

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16 15:01:16 -07:00
Rafael Antognolli
1b42cd52a2 genxml: Rename SF_STATE field to match gen6+.
Rename "Use Point Width State" to "Point Width Source". It accepts the same
values and has the same meaning as gen6+, so lets keep them with the same name
to simplify the code.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16 15:01:16 -07:00
Rafael Antognolli
bd40c71132 i965: aa_line_distance_mode should be before the padding.
It seems that it was never set correctly.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-16 15:01:16 -07:00
Tim Rowley
a6237e4b7f swr/rast: Fix read-back of viewport array index
Binner/clipper read viewport array index from the vertex header as needed.
Move viewport state to BACKEND_STATE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
9b448da60f swr/rast: Refactor includes to limit simdintrin.h usage
Reduces the files rebuilt after modifying simdintrin.h from
84 to 64.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
08a466aec0 swr/rast: Fix read-back of render target array index
The last FE stage can emit render target array index. Currently we only
check to see if GS is emitting it. Moved the state to BACKEND_STATE and
plumbed the driver to set it.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
17cdd1e796 swr/rast: Adjust cast for gcc warning
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
bea00a7b6e swr/rast: Don't transition hottile resolved->dirty during store tiles
Fixes crash when dumping render targets and RT surface has been deleted.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
5c08bfbd17 swr/rast: gen_llvm_types.py support for SIMD256/SIMD512
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
21baadfe58 swr/rast: Properly size GS stage scratch space
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
3695c8ec1e swr/rast: Fix early z / query interaction
For certain cases, we perform early z for optimization. The GL_SAMPLES_PASSED
query was providing erroneous results because we were counting the number
of samples passed before the fragment shader, which did not work if the
fragment shader contained a discard.

Account properly for discard and early z, by anding the zpass mask with
the post fragment shader active mask, after the fragment shader.

Fixes the following piglit tests:
    - occlusion-query-discard
    - occlusion_query_meta_fragments

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
b7eb86c617 swr/rast: Share vertex memory between VS input/output
Removes large simdvertex stack allocation.

Vertex shader must ensure reads happen before writes.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
7f3be3f0b8 swr/rast: Add support for dynamic vertex size for VS output
Add support for dynamic vertex size for the vertex shader output.

Add new state in SWR_FRONTEND_STATE to specify the size.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
8e5d11cd7b swr/rast: SIMD16 FE - improve calcDeterminantIntVertical
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
01eca81cd4 swr/rast: Add support to PA for variable sized vertices
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
b10cdb217a swr/rast: Rework attribute layout
Move fixed attributes to the top and pack single component SGVs.
WIP to support dynamically allocated vertex size.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
36ac8ba511 swr/rast: Remove explicit primitive id slot in the vertex layout
- Remove any special casing in the PS stage when primitive ID is input.
  Treat as a normal attribute that must be set up properly in the FE linkage.
- Remove primitive id from the PS_CONTEXT and TRI_FLAGS

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
8716e0d8b4 swr/rast: Fix invalid 16-bit format traits for A1R5G5B5
Correctly handle formats of <= 16 bits where the component bits don't
add up to the pixel size.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Tim Rowley
a25093de71 swr/rast: Implement JIT shader caching to disk
Disabled by default; currently doesn't cache shaders (fs,gs,vs).

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-06-16 16:20:16 -05:00
Brian Paul
1c33dc77f7 gallium/docs: improve docs for SAMPLE_POS, SAMPLE_INFO, TXQS, MSAA semantics
For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render
target queries, range of postion values, swizzling, etc.  We basically
follow the DX10.1 conventions.

For the TXQS opcode and TGSI_SEMANTIC_SAMPLEID, clarify return value
and type.

For the TGSI_SEMANTIC_SAMPLEPOS system value, clarify the range of
positions returned.

v2: use 'undef' for unused vector components.  Use (0.5, 0.5, undef, undef)
for sample pos when MSAA not applicable.

v3: Add note that OPCODE_SAMPLE_INFO, OPCODE_SAMPLE_POS are not used yet
and the information is subject to change.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-06-16 14:07:31 -06:00
Brian Paul
005c978c5a svga: add some missing SVGA_STATS_* enum values, prefix strings
To fix the build when VMX86_STATS is defined.
Also, some minor whitespace changes to match upstream code.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-06-16 14:06:53 -06:00
Bruce Cherniak
80b587ba27 swr: Don't crash when encountering a VBO with stride = 0.
The swr driver uses vertex_buffer->stride to determine the number
of elements in a VBO. A recent change to the state-tracker made it
possible for VBO's with stride=0. This resulted in a divide by zero
crash in the driver. The solution is to use the pre-calculated vertex
element stream_pitch in this case.

This patch fixes the crash in a number of piglit and VTK tests introduced
by 17f776c27b.

There are several VTK tests that still crash and need proper handling of
vertex_buffer_index.  This will come in a follow-on patch.

v2: Correctly update all parameters for VBO constants (stride = 0).
    Also fixes the remaining crashes/regressions that v1 did
    not address, without touching vertex_buffer_index.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-06-16 13:45:24 -05:00