Commit graph

82384 commits

Author SHA1 Message Date
Jordan Justen
ef06ddb08a anv/pipeline: Set FS URB space to zero if the FS is unused
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-02-28 10:51:38 -08:00
Jordan Justen
45d8ce07a5 anv/pipeline: Set stage URB size to zero if it is unused
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-02-28 10:49:39 -08:00
Samuel Pitoiset
b3efa0a59e gk110/ir: add ld lock/st unlock emission
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-28 19:20:20 +01:00
Ilia Mirkin
aa3b85fd18 nv50,nvc0: bump minimum texture buffer offset alignment
It appears that it actually needs to be aligned to the datum size, so it
was 1 when testing with R8, but it can be as high as 16 with RGBA32.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-02-27 16:26:34 -05:00
Jason Ekstrand
46b7c242da anv/gen7: Clean up the dummy PS case
Fix whitespace and remove dead comments
2016-02-27 11:24:09 -08:00
Jason Ekstrand
e18a2f037a anv/gen7: Set MaximumNumberofThreads in the dummy PS packet 2016-02-27 11:23:56 -08:00
Jason Ekstrand
ad50896c87 anv/gen7: Only try to get the depth format the surface has depth 2016-02-27 11:23:18 -08:00
Jason Ekstrand
4b34f2ccb8 anv/image: Use isl for filling brw_image_param 2016-02-27 10:26:14 -08:00
Jason Ekstrand
bd6470fa6c isl: Add helpers for filling out brw_image_param 2016-02-27 10:26:14 -08:00
Jason Ekstrand
7363024cbd anv: Fill out image_param structs at view creation time 2016-02-27 10:26:14 -08:00
Jason Ekstrand
e9d126f23b anv/image: Add a ussage_mask field to image_view_init
This allows us to avoid doing some unneeded work on the meta paths where we
know that the image view will be used for exactly one thing.  The meta
paths also sometimes do things that aren't quite valid like setting the
array slice on a 3-D texture and we want to limit the number of paths that
need to be able to sensibly handle the lies.
2016-02-27 10:26:14 -08:00
Jason Ekstrand
b4c16fd01a isl: Move isl_image.c to isl_storage_image.c 2016-02-27 10:26:14 -08:00
Jason Ekstrand
eb19d640eb anv: Use isl to fill buffer surface states 2016-02-27 10:26:14 -08:00
Jason Ekstrand
a0cd20eb7f isl: Add a helper for filling a buffer surface state 2016-02-27 10:26:14 -08:00
Jason Ekstrand
9d5b8f7709 anv: Remove unneeded fiels from anv_image_view 2016-02-27 10:26:14 -08:00
Jason Ekstrand
b70a8d40fa anv/state: Remove unused fill_surface_state functions 2016-02-27 10:26:14 -08:00
Jason Ekstrand
ded57c3cca anv: Use ISL to fill out surface states 2016-02-27 10:26:14 -08:00
Jason Ekstrand
4a9b805ce5 anv/device: Store the default MOCS in the device 2016-02-27 10:26:13 -08:00
Jason Ekstrand
d798762cdb isl: Add a function for filling out a surface state 2016-02-27 10:26:13 -08:00
Jason Ekstrand
6b06072ba8 isl: Create per-gen helper libraries for gens 7, 8, and 9 2016-02-27 10:26:13 -08:00
Jason Ekstrand
82d2db80bb genxml: Add MOCS fields to RENDER_SURFACE_STATE
This allows us to set MOCS as a single uint32_t on all platforms.
2016-02-27 10:26:13 -08:00
Jason Ekstrand
452782f68b gen/genX_pack: Add genxml to the pack header path
If you have an out-of-tree build, gen8_pack.h and friends will not be in
the same folder as genX_pack.h so this will be a problem.  We fixed
out-of-tree earlier by adding the genxml folder to the includes for the
vulkan driver.  However, this is not a good long-term solution because we
want to use it in ISL as well.
2016-02-27 10:26:13 -08:00
Ilia Mirkin
e2dce1a340 mesa: add GL_OES_gpu_shader5 and GL_EXT_gpu_shader5 support
The two extensions are identical, and are largely taking bits of already
existing desktop functionality. We continue to do a poor job of
supporting the 'precise' keyword, just like we do on desktop.

This passes the relevant dEQP tests that I could find.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2016-02-27 00:08:28 -05:00
Ilia Mirkin
2875183463 mesa: expose GL_EXT_texture_sRGB_decode on GLES 3.0+
Could be exposed on earlier GLES versions if we supported EXT_sRGB, but
we don't, for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2016-02-26 23:55:45 -05:00
Nanley Chery
265d4c415c isl: Fix isl_surf_get_image_intratile_offset_el()
Consecutive tiles are separated by the size of the tile, not by the
logical tile width.

v2: Remove extra subtraction (Ville)
    Add parenthesis (Jason)
v3: Update the unit tests for the function

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-02-26 16:59:36 -08:00
Ian Romanick
585b18f305 i965/cfg: Fix comment list punctuation
Trivial

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
2016-02-26 16:51:27 -08:00
Ian Romanick
5bfb302783 i965/cfg: Split out dead control flow paths to simplify both paths
v2: Fix some bad indentation.  Suggested by Curro.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-26 16:51:27 -08:00
Ian Romanick
2513a20240 i965/cfg: Don't handle fully empty if/else/endif
This will now never occur.  The empty if-else part would have already
been removed leaving an empty if-endif part.

No shader-db changes.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-26 16:51:27 -08:00
Ian Romanick
69bb063ec2 i965/cfg: Eliminate an empty then-branch of an if/else/endif
On BDW,

total instructions in shared programs: 8448571 -> 8448367 (-0.00%)
instructions in affected programs: 21000 -> 20796 (-0.97%)
helped: 116
HURT: 0

v2: Remove spurious attempt to combine the if_block with the (removed!)
else_block.  Suggested by Matt and Curro.  Correct the comment
describing what the new pass does.  Suggested by Matt.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-26 16:51:27 -08:00
Ian Romanick
c7deee69ea i965/cfg: Track prev_block and prev_inst explicitly in the whole function
This provides a trivial simplification now, and it makes some future
changes more straight forward.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-26 16:51:27 -08:00
Ian Romanick
70cf0eb5c7 i965/cfg: Slightly rearrange dead_control_flow_eliminate
'git diff -w' is a bit more illustrative.  A couple declarations were
moved, the continue was removed, and the code was reindented.  This will
simplify future changes.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-26 16:51:27 -08:00
Thomas Hindoe Paaboel Andersen
6bb6b5c341 anv: remove stray ; after if
Both logic and indentation suggests that the ; were not intended here.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-02-26 16:05:28 -08:00
Jason Ekstrand
b7bc52b5b1 anv/gen8: Emit the 3DSTATE_PS_BLEND packet 2016-02-26 16:04:48 -08:00
Kenneth Graunke
a0294c2cf3 i965: Simplify brw_nir_lower_vue_inputs() slightly.
The same code appeared in both branches; pull it above the if statement.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
8151003ade i965: Avoid recalculating the normal VUE map for IO lowering.
The caller already computes it.  Now that we have stage specific
functions, it's really easy to pass this in.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
15b3639bf1 i965: Avoid recalculating the tessellation VUE map for IO lowering.
The caller already computes it.  Now that we have stage specific
functions, it's really easy to pass this in.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
cfbd9831f8 i965: Eliminate brw_nir_lower_{inputs,outputs,io} functions.
Now that each stage is directly calling brw_nir_lower_io(), and we have
per-stage helper functions, it makes sense to just call the relevant one
directly, rather than going through multiple switch statements.

This also eliminates stupid function parameters, such as the two that
only apply to vertex attributes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
b96ddd2e52 i965: Split brw_nir_lower_inputs/outputs into per-stage functions.
These functions are both giant switch statements where most cases don't
overlap at all.  Let's put the bulk of the work in per-stage helpers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
d33c478bed i965: Remove catch-all nir_lower_io call with specific cases.
Most cases already call nir_lower_io explicitly for input and output
lowering.  This catch all isn't very useful anymore - we can just add it
to the remaining cases.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
51f8797993 i965: Move optimizations from brw_nir_lower_io to brw_postprocess_nir.
This simplifies things.  Every caller of brw_nir_lower_io() immediately
calls brw_postprocess_nir().  The only real change this will have is
that we get an extra brw_nir_optimize() call when compiling compute
shaders, but that seems fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
dcd4a841e9 i965: Always do NIR IO lowering at specialization time.
We've now hit literally every case other than geometry shaders (and
compute shaders, but those are a no-op).  So, let's just move geometry
shaders over too and be done with it.

The only advantage to doing this at link time was to save the expense
of running the pass on recompiles.  But we're already running a lot of
passes, and the extra code complexity isn't worth it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Kenneth Graunke
fa7135107f i965: Make an is_scalar boolean in brw_compile_gs().
Shorter than compiler->scalar_stage[MESA_SHADER_GEOMETRY], which can
help with line-wrapping.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Jason Ekstrand
b3cb6e78aa i965/nir: Do lower_io late for fragment shaders
The Vulkan driver wants to be able to delete fragment outputs that are
beyond key.nr_color_regions; this is a lot easier if we lower outputs at
specialization time rather than link time.

(Rationale added to commit message by Ken)

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-02-26 15:55:59 -08:00
Jordan Justen
7428e6f86a i965: Set dest type to UW for several send messages
Without this, on SIMD 16 the send instruction destination will appear
to write more than one destination register, causing the simulator to
report an error.

Of course, the send instruction can actually write more than one
destination register regardless of the type set for the destination,
so this is a bit strange.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-26 12:03:56 -08:00
Samuel Pitoiset
aad48f8691 nvc0: rework nvc0_compute_validate_program()
Reduce the amount of duplicated code by re-using
nvc0_program_validate(). While we are at it, change the prototype
to return void and remove nvc0_compute.h which is now useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-26 14:00:27 +01:00
Samuel Pitoiset
e1f5c76047 nvc0: make sure to validate compute global buffers on Fermi
No reason to not validate those global buffers and this might avoid
fails if someone try to use the global memory from compute programs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-26 14:00:23 +01:00
Samuel Pitoiset
dcf7938833 nvc0: move nvc0_validate_global_residents() to nvc0_compute.c
While we are at it, rename it to nvc0_compute_validate_globals() and
update its prototype.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-26 14:00:18 +01:00
Derek Foreman
d085a5dff5 egl/wayland: Try to use wl_surface.damage_buffer for SwapBuffersWithDamage
Since commit d1314de293 we ignore
damage passed to SwapBuffersWithDamage.

Wayland 1.10 now has functionality that allows us to properly
process those damage rectangles, and a way to query if it's
available.

Now we can use wl_surface.damage_buffer and interpret the incoming
damage as being in buffer co-ordinates.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
2016-02-26 11:49:09 +00:00
Dave Airlie
840aa52f50 virgl: add missing CAP turned off. 2016-02-26 04:03:09 +00:00
Miklós Máté
847f1cc698 program: Remove extra reference_program()
It was already done in get_mesa_program()

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-02-25 22:02:50 +01:00