Commit graph

82384 commits

Author SHA1 Message Date
Bas Nieuwenhuizen
fd0a7a382f radeonsi: Add barrier before writing the tess factors.
The factors may be stored to LDs by another invocation than
the invocation for vertex 0.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
fee3160af9 radeonsi: Enable dynamic HS.
This allows running the TES on different CU's than the
TCS which results in performance improvements.

v2: Only write the control word from one invocation.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
26f436132b radeonsi: Remove LDS layout user SGPR's from TES.
They are unused.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
a4e2146a9d radeonsi: Use buffer loads and stores for passing data from TCS to TES.
We always try to use 4-component loads, as LLVM does not combine loads
and they bypass the L1 cache.

We can't use a similar strategy for stores and this is especially
notable with the tess factors, as they are often set with separate
MOV's per component in the TGSI.

We keep storing to LDS and the LDS space, so we can load the outputs
later, either due to the shader, of for wrting the tess factors.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
6217716e8f radeonsi: Store inputs to memory when not using a TCS.
We need to copy the VS outputs to memory. I decided to do this
using a shader key, as the value depends on other shaders.

I also switch the fixed function TCS over to monolithic, as
otherwisze many of the user SGPR's need to be passed to the
epilog, which increases register pressure, or complexity to
avoid that. The main body of the fixed function TCS is not
that interesting to precompile anyway, since we do it on
demand and it is very small.

v2: Use u_bit_scan64.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
7846fa8768 radeonsi: Add offchip buffer address calculation.
Instead of creating a memory area per patch and per vertex, we put
the same attribute of every vertex & patch together. Most loads
and stores access the same attribute across all lanes, only for
different patches and vertices.

For the TCS this results in tightly packed data for 4-component
stores.

For the TES this is not the case as within a patch the loads
often also access the same vertex. However if there are < 4
vertices/patch, this still results in a reduction of the number
of cache lines. In the LDS situation we only do better than worst
case if the data per patch < 64 bytes, which due to the
tessellation factors is pretty much never.

We do not use hardware swizzling for this. It would slightly reduce
the number of executed VALU instructions, but I had issues with
increased wait times that I haven't been able to solve yet.
Furthermore, the tbuffer_store intrinsic does not support both
VGPR offset and an index, so we have a problem storing
indirectly indexed outputs. This can be solved by temporarily
storing arrays in LDS and then copying them, but I don't think
that is worth the effort. The difference in VALU cycles
hardware swizzling gives is about 0.2% of total busy cycles.
That is without handling the array case.

I chose for attributes instead of components as they are often
accessed together, and the software swizzling takes VALU cycles
for calculating offsets.

v2: - Rename functions to get_tcs_tes_buffer_address.
    - multiply by 16 as late as possible.
    - Use  tgsi_full_src_register_from_dst.
    - Remove some bad comments.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
c49e68dc4b radeonsi: Add user SGPR for the layout of the offchip buffer.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
d9a0c54f6f radeonsi: Use correct parameter index for LS_OUT_LAYOUT.
This happens to be in the right position, but that changes
when TCS/TES get new parameters.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
3e7a7a9a65 radeonsi: Add buffer load functions.
v2: - Use llvm.admgcn.buffer.load instrinsics for new LLVM.
    - Code style fixes.

v3: - Code style fix.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
9fdb778702 radeonsi: Define build_tbuffer_store_dwords earlier to support new users.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
5c34562d7c radeonsi: Add offchip tessellation parameters.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Bas Nieuwenhuizen
d27ff7d683 radeonsi: Add buffer for offchip storage between TCS and TES.
The buffer is quite large, but should only be allocated if the
application uses tessellation. Most non-games don't.

v2: - Use the correct register for SI.
    - Add define for block size.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-26 22:07:04 +02:00
Rob Clark
6e51fe75a4 tgsi: fix coverity out-of-bounds warning
CID 1271532 (#1 of 1): Out-of-bounds read (OVERRUN)34. overrun-local:
Overrunning array of 2 16-byte elements at element index 2 (byte offset
32) by dereferencing pointer &inst.Dst[i].

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-26 15:17:49 -04:00
Rob Clark
3d66ba971e tgsi: fix out of bounds access
Not sure why coverity calls this an out-of-bounds read vs out-of-bounds
write.

CID 1358920 (#1 of 1): Out-of-bounds read (OVERRUN)9. overrun-local:
Overrunning array r of 3 16-byte elements at element index 3 (byte
offset 48) using index chan (which evaluates to 3).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-26 15:17:49 -04:00
Anuj Phogat
0c02d7002d i965: Don't use fast copy blit in case of logical operations other than GL_COPY
XY_FAST_COPY_BLT command doesn't have a field for raster operation. So, fall
back to using XY_SRC_COPY_BLT to handle those cases.

Fixes piglit test gl-1.1-xor-copypixels when fast copy blit is enabled
for all tiling formats.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-26 10:57:09 -07:00
Anuj Phogat
97f0f91cc1 i965/gen9: Remove the halign/valign field setup code in fast copy blit
Experimentation with different values of src/dst horizontal/vertical
alignment showed that these fileds are not used on gen9 hardware.

A recent update in graphics specs has removed these fields from
XY_FAST_COPY_BLT command.

Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Chad Versace <chad.versace@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2016-05-26 10:57:09 -07:00
Samuel Pitoiset
c52e92ec3a nvc0: allow to monitor MP perf counters with compute shaders
To read out MP perf counters we use a compute shader and need to upload
input data like a 64-bits addr used to store the values and a sequence
ID for synchronization. Currently, this input data is uploaded as user
uniforms which means that it's sticked to c0[], but if a compute shader
from a real application is used, monitoring those performance counters
will just overwrite some data and miserably crash.

Instead, sticking the 64-bits addr and the sequence into the driver
constant buffer seems like much better and will allow to monitor
counters with GL 4.3 apps.

Tested on GF119 and GK110, but should not hurt anything on GK104.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-26 19:34:57 +02:00
Kristian Høgsberg Kristensen
329d115ac6 mesa: Move robustness code to main/robustness.c
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-26 09:37:17 -07:00
Kristian Høgsberg Kristensen
d7d729b965 docs: Mark GL_KHR_robustness done for GLES3.2 as well
Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-26 09:36:36 -07:00
Plamena Manolova
a0674ce5c4 egl: Additional attribute validation for eglCreatePbufferSurface
eglCreatePbufferSurface should generate an EGL_BAD_MATCH error if:
1: The EGL_TEXTURE_FORMAT attribute is EGL_NO_TEXTURE and EGL_TEXTURE_TARGET
is something other than EGL_NO_TEXTURE
2: EGL_TEXTURE_FORMAT is something other than EGL_NO_TEXTURE and
EGL_TEXTURE_TARGET is EGL_NO_TEXTURE.

This fixes the dEQP-EGL.functional.negative_api.create_pbuffer_surface test.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2016-05-26 08:02:48 -07:00
Marek Olšák
8539c9bf31 gallium/radeon: add the kernel version into the renderer string
Example:
Gallium 0.4 on AMD TONGA (DRM 3.2.0 / 4.5.0, LLVM 3.9.0)

My kernel version is pretty long already (4.5.0-amd-01025-g32791c1)
and adding "kernel" into the string would make too it long for glxinfo
to display.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-05-26 16:53:46 +02:00
Marek Olšák
53f33619a4 winsys/amdgpu: add back multithreaded command submission
Ported from the initial amdgpu winsys from the private AMD branch.

The thread creates the buffer list, submits IBs, and cleans up
the submission context, which can also destroy buffers.

3-5% reduction in CPU overhead is expected for apps submitting a lot
of IBs per frame. This is most visible with DMA IBs.

v2: use a semaphore instead of a busy loop in amdgpu_ws_queue_cs
    add another amdgpu_cs_sync_flush call into amdgpu_bo_map

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-05-26 16:43:45 +02:00
Lars Hamre
c626a86586 gallium/tgsi: use _mesa_roundevenf in micro_rnd
Fixes the following piglit tests (for softpipe):

/spec/glsl-1.30/execution/built-in-functions/...
fs-roundeven-float
fs-roundeven-vec2
fs-roundeven-vec3
fs-roundeven-vec4
vs-roundeven-float
vs-roundeven-vec2
vs-roundeven-vec3
vs-roundeven-vec4

/spec/glsl-1.50/execution/built-in-functions/...
gs-roundeven-float
gs-roundeven-vec2
gs-roundeven-vec3
gs-roundeven-vec4

Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-26 07:59:15 -06:00
Emil Velikov
d519f59a9f .mailmap: use Jakob Bornecrantz's personal email
The VMware one is bouncing.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-05-26 13:57:32 +01:00
Ilia Mirkin
f998e5dc6b nvc0: add note about where the viewport mask would go
Not piping this all the way through yet, but no better place to note
this down. This will can be used with NV_viewport_array2.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-26 08:46:29 -04:00
Ilia Mirkin
b634936d3b nvc0: enable 32 textures on kepler+
For fermi, this likely will require use of linked tsc mode. However on
bindless architectures, we can have as many as we want. As it stands,
the AUX_TEX_INFO has 32 teture handles reserved.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-05-26 08:46:13 -04:00
Alejandro Piñeiro
2ed9563e79 glsl: add unit tests data vertex/expected outcome for uninitialized warning
v2: fix 025 test. Add three more tests (Ian Romanick)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-26 09:19:36 +02:00
Alejandro Piñeiro
eee00274fa glsl: add warning-test
It executes compiler-glsl on all the available shaders, and it checks
that the outcome is the expected.

Bash code based on the already existing optimization-test

v2: rebasing: use --version option

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-26 09:19:17 +02:00
Alejandro Piñeiro
68c23d2d04 glsl: add just-log option for the standalone compiler.
Add an option in order to ask to just print the InfoLog, without any
header or separator. Useful if we want to use the standalone compiler
to track only the warning/error messages.

v2: all printfs goes on its own line (Ian Romanick)
v3: rebasing: move just_log to standalone.h/cpp

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-26 08:46:05 +02:00
Alejandro Piñeiro
66ff04322e glsl: do not raise uninitialized warning with out function parameters
It silence by default warnings with function parameters, as the
parameters need to be processed in order to have the actual and the
formal parameter, and the function signature. Then it raises the
warning if needed at verify_parameter_modes where other in/out/inout modes
checks are done.

v2: fix comment style, multi-line condition style, simplify check,
    remove extra blank (Ian Romanick)
v3: inout function parameters can raise the warning too (Ian
    Romanick)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-26 08:39:17 +02:00
Alejandro Piñeiro
b9f90ef652 glsl: add a empty set_is_lhs on ast_node
Just to allow to call set_is_lhs on any ast_node without a casting. Useful
when processing a ast_node list that we know it contain ast_expression.

v2: comment out new_value to avoid unused parameter warning (Ian Romanick)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-26 08:39:07 +02:00
Dave Airlie
5b2675093e glsl: handle implicit sized arrays in ssbo
The current code disallows unsized arrays except at the end of
an SSBO but it is a bit overzealous in doing so.

struct a {
	int b[];
	int f[4];
};

is valid as long as b is implicitly sized within the shader,
i.e. it is accessed only by integer indices.

I've submitted some piglit tests to test for this.

This also has no regressions on piglit on my Haswell.
This fixes:
GL45-CTS.shader_storage_buffer_object.basic-syntax
GL45-CTS.shader_storage_buffer_object.basic-syntaxSSO

This patch moves a chunk of the linker code down, so
that we don't link the uniform blocks until after we've
merged all the variables. The logic went something like:

Removing the checks for last ssbo member unsized from
the compiler and into the linker, meant doing the check
in the link_uniform_blocks code. However to do that the
array sizing had to happen first, so we knew that the
only unsized arrays were in the last block. But array
sizing required the variable to be merged, otherwise
you'd get two different array sizes in different
version of two variables, and one would get lost
when merged. So the solution was to move array sizing
up, after variable merging, but before uniform block
visiting.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-26 12:42:10 +10:00
Dave Airlie
4d70fd1bc7 glsl: fix error message on uniform block mismatch
This looks like a cut-paste from above.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-26 12:40:41 +10:00
Dave Airlie
c952c0e713 glsl/ast: assign explicit_xfb_buffer from correct place
This fixes:
GL44-CTS.tessellation_shader.tessellation_control_to_tessellation_evaluation.data_pass_through

As the OUT_TC interface structures weren't matching because
one of them had explicit_xfb_buffer set when it shouldn't.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-26 12:17:03 +10:00
Bruce Cherniak
c8835a5924 swr: [rasterizer] Correctly select optimized primitive assembly.
Indexed primitives were always using cut-aware primitive assembly,
whether primitive_restart was enabled or not.  Correctly pass down
primitive_restart and select optimized PA when possible.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-05-25 18:47:16 -05:00
Kenneth Graunke
978ab88858 docs: Mention i965/gen8+ supports GL 4.2 in release notes. 2016-05-25 14:22:56 -07:00
Kenneth Graunke
72ba9c3160 docs: Update GL_OES_copy_image status. 2016-05-25 14:22:30 -07:00
Kenneth Graunke
0f0f357b77 i965: Enable OES_copy_image (and EXT) on Gen8+ and Baytrail.
For now, only enable it on platforms that actually support ETC2.

At this point, Broadwell is only failing 5 (out of 8358) dEQP tests:
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.
   srgb8_alpha8_r11f_g11f_b10f.renderbuffer_to_texture3d
   srgb8_alpha8_rgb10_a2ui.renderbuffer_to_cubemap
   srgb8_alpha8_rgb10_a2ui.renderbuffer_to_renderbuffer
   srgb8_alpha8_rgb10_a2.renderbuffer_to_texture2d
   srgb8_alpha8_rgb9_e5.renderbuffer_to_texture3d

These fail with all methods (meta, blorp, blitter, memcpy).

All are blacklisted from the Android mustpass list, which makes me
wonder whether there's an issue with the tests.  The formats in
question work with other targets, and the targets in question work
with other formats...

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Kenneth Graunke
88a630121d i965: Implement a BLORP path for CopyImage and prefer it over Meta.
We're dropping Meta in favor of BLORP everywhere we can.

This also fixes bugs when copying cubemaps to 2D, which is currently
broken in the meta pass.  BLORP just works.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94198
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Kenneth Graunke
2822c8a078 i965: Make the CopyImage BLT path bail for stencil images.
The BLT can't handle S8 because it's W-tiled (at least without
additional funny business, and I'm not sure we care).  Disallow
it so it falls back to the CPU path, which works.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Kenneth Graunke
c51702bdc8 i965: Also copy stencil miptree data.
The Meta path handles this, but the CPU/BLT fallbacks did not.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Kenneth Graunke
45d6818021 i965: Make a helper function for CopyImage of a miptree.
Currently, it only contains the BLT/CPU fallbacks, so the name is a bit
too generic.  But eventually this will use BLORP as well, at which point
the name will make more sense.

The next patch will introduce a second call.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Kenneth Graunke
2dc98d9a15 i965: Combine src/dest tex vs. rb checks in intel_copy_image_sub_data.
This simplifies things a little - now we only have one (tex or rb?)
if-ladder for src, and a second for dst, rather than four.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Kenneth Graunke
1b39c5efca i965: Account for MinLayer in CopyImageSubData's blitter/CPU paths.
Fixes Piglit's arb_copy_image-texview test with the Meta path disabled
(so we hit the blitter/CPU fallback paths).

v2: Add MinLayer even for cube maps (suggested by Ilia).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
2016-05-25 14:17:29 -07:00
Rob Clark
231dcb19f9 freedreno/ir3: cmdline compiler for glsl
Use glsl/libstandalone.la to add support for taking glsl src files (in
addition to .tgsi) as input.  Then glsl->nir and feed the result into
the ir3 backend as normal.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-25 16:31:15 -04:00
Rob Clark
0f982bb67d glsl: split out libstandalone
Split standalone glsl_compiler into a libstandalone.la and a thin
main.cpp.  This way drivers can re-use the glsl standalone frontend in
their own standalone compilers.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-05-25 16:31:15 -04:00
Rob Clark
ec434d940d android: drop build of standalone glsl_compiler
It's only a tool for debugging the glsl compiler, and should not be
installed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rob Herring <robh@kernel.org>
Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-05-25 16:31:15 -04:00
Matt Turner
61847d7708 i965: Mark fallthrough in switch statement.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2016-05-25 12:44:34 -07:00
Matt Turner
83c6749ddb i965: Assert that a depth_mt exists when using HiZ.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2016-05-25 12:44:34 -07:00
Matt Turner
4a5e92ac70 nir: Strengthen assertion that 'out' is nonnull.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2016-05-25 12:44:34 -07:00