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radeonsi: Remove LDS layout user SGPR's from TES.
They are unused. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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a4e2146a9d
commit
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3 changed files with 10 additions and 13 deletions
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@ -5414,9 +5414,7 @@ static void create_function(struct si_shader_context *ctx)
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case PIPE_SHADER_TESS_EVAL:
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params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
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params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
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params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
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num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
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num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
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if (shader->key.tes.as_es) {
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params[ctx->param_oc_lds = num_params++] = ctx->i32;
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@ -108,12 +108,12 @@ enum {
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/* both TCS and TES */
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SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
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SI_SGPR_TCS_OUT_OFFSETS,
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SI_SGPR_TCS_OUT_LAYOUT,
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SI_TES_NUM_USER_SGPR,
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/* TCS only */
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SI_SGPR_TCS_IN_LAYOUT = SI_TES_NUM_USER_SGPR,
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SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
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SI_SGPR_TCS_OUT_LAYOUT,
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SI_SGPR_TCS_IN_LAYOUT,
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SI_TCS_NUM_USER_SGPR,
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/* GS limits */
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@ -155,26 +155,27 @@ enum {
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*/
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SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
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/* TCS only parameters. */
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/* Offsets where TCS outputs and TCS patch outputs live in LDS:
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* [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
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* [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
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*/
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SI_PARAM_TCS_OUT_OFFSETS, /* for TCS & TES */
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SI_PARAM_TCS_OUT_OFFSETS,
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/* Layout of TCS outputs / TES inputs:
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* [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
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* [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
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* [26:31] = gl_PatchVerticesIn, max = 32
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*/
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SI_PARAM_TCS_OUT_LAYOUT, /* for TCS & TES */
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SI_PARAM_TCS_OUT_LAYOUT,
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/* Layout of LS outputs / TCS inputs
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* [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
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* [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
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*/
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SI_PARAM_TCS_IN_LAYOUT, /* TCS only */
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SI_PARAM_TCS_IN_LAYOUT,
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/* TCS only parameters. */
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SI_PARAM_TCS_OC_LDS,
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SI_PARAM_TESS_FACTOR_OFFSET,
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SI_PARAM_PATCH_ID,
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@ -201,10 +201,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx,
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radeon_emit(cs, tcs_in_layout);
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/* Set them for TES. */
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radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
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radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
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radeon_emit(cs, offchip_layout);
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radeon_emit(cs, tcs_out_offsets);
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radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26));
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}
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static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
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