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Author SHA1 Message Date
Georg Lehmann
2ac7e6614a nir: unify lower_bitfield_extract with has_bfe 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>
 2023-08-22 12:08:37 +00:00
Georg Lehmann
34c3f81614 nir: unify lower_bitfield_insert with has_{bfm,bfi,bitfield_select} 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24662>
 2023-08-22 12:08:37 +00:00
Friedrich Vock
bfb55d0266 ac/sqtt,radv/sqtt: Add and use marker for separate RT compilation 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
3d3d5c4bc3 radv/sqtt: Handle separately-compiled RT pipelines 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
1cd9525b18 radv/sqtt: Write LDS size metadata in code objects 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
7809fb9e49 radv/sqtt: Unregister records based on hash 
RT pipelines have multiple hashes used in records, so don't always use
the pipeline hash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
3ed4cca883 radv/sqtt: Move record filling to helper function 
RT shaders construct records differently, but this piece of code is
common to all types of pipelines.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
b4a704b42a ac/rgp: Add metadata for separate-compiled RT stages 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
0c4e92bf3e ac/rgp: Write lds_size metadata 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Friedrich Vock
be0e3e8e09 ac/sqtt,radv: Split internal and API hash in PSO correlations 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24371>
 2023-08-22 11:33:11 +00:00
Samuel Pitoiset
a29e2c6fbc aco: implement create_tcs_jump_to_epilog() 
This implements jumping from the main TCS to the epilog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
 2023-08-22 06:10:32 +00:00
Samuel Pitoiset
131c3aa3dc radv: add tcs_out_patch_fits_subgroup to radv_tcs_epilog_key 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
 2023-08-22 06:10:32 +00:00
Samuel Pitoiset
65191bb351 radv: declare shader arguments for TCS epilogs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
 2023-08-22 06:10:32 +00:00
Samuel Pitoiset
d0808b22cb radv: stop declaring the scratch offset argument for TCS epilogs 
ACO skip it for epilogs now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
 2023-08-22 06:10:32 +00:00
Samuel Pitoiset
6ad8abf7aa radv: use the maximum possible workgroup size for TCS epilogs 
It's similar to when the patch control points value is dynamic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24643>
 2023-08-22 06:10:32 +00:00
Tatsuyuki Ishi
6c5512568b radv/amdgpu: Do not pass in a BO handle when clearing PRT VA region. 
This field is invalid to access for virtual BOs.

Fixes: a931d5a4a4 ("radv/winsys: clear the PRT VA range when destroying a virtual BO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24805>
 2023-08-21 17:24:35 +00:00
Konstantin Seurer
2943bc34e9 radv: Remove leaf_args::dst_offset 
We can use first_id instead.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24756>
 2023-08-21 12:45:06 +00:00
Konstantin Seurer
90a24c7cb3 radv: Add internal_nodes_offset to scratch_layout 
It shouldn't be a part of bvh_state.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24756>
 2023-08-21 12:45:06 +00:00
Samuel Pitoiset
b8b42be555 radv/amdgpu: add support for submitting external IBs with the chained path 
External IBs are currently only used for DGC. With the chained path,
these IBs will only be used to workaround missing IB2 packet on the
compute queue, which is rare enough to care about chaining inside CS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24207>
 2023-08-21 10:52:13 +00:00
Samuel Pitoiset
33f584f033 radv/amdgpu: allow to execute external IBs on the compute queue 
IB2 isn't supported on ACE, so external IBs should be submitted as IB1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24207>
 2023-08-21 10:52:13 +00:00
Samuel Pitoiset
e3fae01730 Revert "radv/amdgpu: skip adding per VM BOs for sparse during CS BO list build" 
This reverts commit 51caece74c.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24774>
 2023-08-21 09:42:51 +00:00
Samuel Pitoiset
f67eb9ce07 Revert "radv/amdgpu: workaround a kernel bug when replacing sparse mappings" 
This workaround was added temporarily but it can actually cause
stuttering in some games like Forza Horizon 5.

The kernel fix
(https://lists.freedesktop.org/archives/amd-gfx/2023-June/094648.html)
landed in some stable kernels (5.15.121+, 6.1.40+ and 6.4.5+). Sadly,
older stable kernels don't have it, so you might experiment random GPU
hangs in games that use sparse mapping. Please ensure your kernel is
up-to-date for the best experience.

This reverts commit 9b00867327.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9443
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24774>
 2023-08-21 09:42:51 +00:00
Marek Olšák
905a00f10a ac/surface: add radeon_surf::u::gfx9::uses_custom_pitch 
so that we don't try to guess when the pitch is overridden

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24759>
 2023-08-19 19:36:56 +00:00
Marek Olšák
5d19a0a19b Revert "ac: don't call ac_query_pci_bus_info from ac_query_gpu_info" 
This reverts commit a48642400b.

Instead, add a new parameter require_pci_bus_info to control the behavior.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24759>
 2023-08-19 19:36:55 +00:00
Samuel Pitoiset
b78ea2a38f radv: stop copying if VS or TES uses the InvocationID built-in 
It's only allowed in TCS or GS which means the src shader stage
value is always FALSE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24691>
 2023-08-18 09:31:23 +00:00
Samuel Pitoiset
d547c996ae radv: simplify declaring VS specific input SGPRs 
stage/previous_stage are actually useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24691>
 2023-08-18 09:31:23 +00:00
Samuel Pitoiset
525143d01a radv: remove unused param from radv_pipeline_init_multisample_state() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24691>
 2023-08-18 09:31:23 +00:00
Samuel Pitoiset
1cf840fb3e radv: remove radv_cmd_buffer::cached_vertex_formats 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24770>
 2023-08-18 10:23:45 +02:00
Samuel Pitoiset
c136169062 radv: fix emitting TCS epilogs for GFX6-9 
The number of SGPRs need to be adjusted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24747>
 2023-08-18 07:52:22 +00:00
Samuel Pitoiset
f9a9471caf radv: add missing comment about TCS_OFFCHIP_LAYOUT_LSHS_VERTEX_STRIDE 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24745>
 2023-08-18 07:11:26 +00:00
Samuel Pitoiset
c6a56e6b3d radv: reduce TCS_OFFCHIP_LAYOUT_NUM_PATCHES to 6-bits 
RADV clamps the number of tess patches to 40.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24745>
 2023-08-18 07:11:26 +00:00
Faith Ekstrand
b5d6b7c402 nir: Drop most uses if nir_instr_rewrite_src() 
Generated by the following semantic patch:

    @@
    expression I, S, D;
    @@

    -nir_instr_rewrite_src(I, S, nir_src_for_ssa(D));
    +nir_src_rewrite(S, D);

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24729>
 2023-08-18 01:00:15 +00:00
Faith Ekstrand
de063a1481 nir: Drop most uses of nir_instr_rewrite_src_ssa() 
Generated with the following semantic patch:

    @@
    expression I, S, D;
    @@

    -nir_instr_rewrite_src_ssa(I, S, D);
    +nir_src_rewrite(S, D);

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24729>
 2023-08-18 01:00:15 +00:00
Caio Oliveira
39e24082fc radv: Use nir_opt_reuse_constants() 
Right now, this won't change much the shaders since most of the NIR constants
are reused in the NIR generated by SPIR-V, but will make radv resilient to
when that behavior change.

```
RADV GFX1100 results for radv fossils:

Totals:
Instrs: 71623585 -> 71623708 (+0.00%); split: -0.00%, +0.00%
CodeSize: 369326156 -> 369324312 (-0.00%); split: -0.00%, +0.00%
SpillSGPRs: 13576 -> 13586 (+0.07%)
Latency: 632889681 -> 632887831 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 81674616 -> 81674859 (+0.00%); split: -0.00%, +0.00%
SClause: 2409601 -> 2409593 (-0.00%); split: -0.00%, +0.00%
Copies: 4063438 -> 4063579 (+0.00%); split: -0.00%, +0.01%
Branches: 1196703 -> 1196723 (+0.00%)
PreSGPRs: 4242897 -> 4243061 (+0.00%); split: -0.00%, +0.00%
PreVGPRs: 3926739 -> 3926742 (+0.00%)

Totals from 217 (0.16% of 133461) affected shaders:
Instrs: 353567 -> 353690 (+0.03%); split: -0.04%, +0.07%
CodeSize: 1790200 -> 1788356 (-0.10%); split: -0.15%, +0.04%
SpillSGPRs: 8 -> 18 (+125.00%)
Latency: 5152817 -> 5150967 (-0.04%); split: -0.05%, +0.01%
InvThroughput: 664273 -> 664516 (+0.04%); split: -0.03%, +0.06%
SClause: 10164 -> 10156 (-0.08%); split: -0.10%, +0.02%
Copies: 24225 -> 24366 (+0.58%); split: -0.32%, +0.90%
Branches: 7116 -> 7136 (+0.28%)
PreSGPRs: 13351 -> 13515 (+1.23%); split: -0.16%, +1.39%
PreVGPRs: 11583 -> 11586 (+0.03%)
```

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5282>
 2023-08-17 14:58:02 +00:00
Rhys Perry
cf796aa885 radv: vectorize scratch access 
fossil-db (gfx1100):
Totals from 20 (0.01% of 133461) affected shaders:
Instrs: 49421 -> 49134 (-0.58%)
CodeSize: 251668 -> 249604 (-0.82%); split: -0.83%, +0.01%
Latency: 178126 -> 178412 (+0.16%); split: -0.16%, +0.32%
InvThroughput: 23565 -> 23646 (+0.34%); split: -0.05%, +0.39%
VClause: 957 -> 943 (-1.46%)
Copies: 5770 -> 5801 (+0.54%); split: -0.36%, +0.90%
PreVGPRs: 1368 -> 1359 (-0.66%)

Regressions seem to be a couple of cases of bad RA luck.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry
81641b0155 radv: vectorize RT stack access 
fossil-db (gfx1100):
Totals from 10 (0.01% of 133461) affected shaders:
MaxWaves: 176 -> 174 (-1.14%)
Instrs: 39260 -> 38710 (-1.40%)
CodeSize: 202272 -> 197288 (-2.46%)
VGPRs: 888 -> 900 (+1.35%)
Latency: 82306 -> 81762 (-0.66%); split: -0.68%, +0.02%
InvThroughput: 11182 -> 11158 (-0.21%); split: -0.52%, +0.30%
VClause: 721 -> 700 (-2.91%)
SClause: 1147 -> 1148 (+0.09%); split: -0.17%, +0.26%
Copies: 3625 -> 3891 (+7.34%)
PreVGPRs: 819 -> 845 (+3.17%); split: -0.37%, +3.54%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24350>
 2023-08-16 19:11:26 +00:00
Rhys Perry
5a7efccdc3 radv/gfx11: re-enable 0001/1110 clear values 
Since 87444bb7ab, vi_alpha_is_on_msb always
returned false here. The new version matches radeonsi.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Rhys Perry
19f73f8eb4 radv: support 128bpp comp-to-single with all colors 
Previously, it was restricted to clear colors where R==G==B, but it seems
to work if that isn't the case.

This restriction was probably a leftover from before comp-to-single.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Rhys Perry
e2c7ce3719 radv: fix 128bpp comp-to-single clears 
We were clearing GB to A, instead of R.

This fixes some red tinting in Overwatch 2 when shadow quality is set to
"Ultra".

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 7451eb1d61 ("radv: implement DCC fast clears with comp-to-single")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9446
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Rhys Perry
405f3bf990 radv: disable 64-bit color attachments 
These work in some circumstances (dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc),
but I'm not sure if they work in all, blending certainly doesn't work and
this probably wasn't intended in the first place.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 01bd012edd ("amd: fix 64-bit integer color image clears")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
 2023-08-16 18:38:24 +00:00
Faith Ekstrand
b64da56b1a nir: s/nir_instr_ssa_def/nir_instr_def/ 
Generated by sed:

    sed -i -e 's/nir_instr_ssa_def/nir_instr_def/g' src/**/*.h src/**/*.c src/**/*.cpp

Suggested-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24703>
 2023-08-15 17:44:27 +00:00
Konstantin Seurer
a02b5138a7 radv/rt: Rename traversal_shader to traversal_shader_addr 
It's more in line with shader_addr and uniform_shader_addr as well as
the user data name.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23565>
 2023-08-15 11:11:16 +02:00
Konstantin Seurer
c291f612cb radv/rt: Rename shader_pc and next_shader 
The names basically had the same meaning. Changing them to
uniform_shader_addr and shader_addr makes it clear, that
uniform_shader_addr is the jump target and shader_addr is the next
shader executed by this invocation.

The next_ prefix is dropped since both are input and output variables.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23565>
 2023-08-15 11:11:16 +02:00
Faith Ekstrand
4695bebc79 nir: Drop nir_dest 
Instead, we replace every use of it with nir_def.  Most of this commit
was generated by sed:

   sed -i -e 's/dest.ssa/def/g' src/**/*.h src/**/*.c src/**/*.cpp

A few manual fixups were required in lima and the nir_legacy code.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
 2023-08-14 21:22:53 +00:00
Faith Ekstrand
6c1d32581a nir: Drop nir_alu_dest 
Instead, we replace it directly with nir_def.  We could replace it with
nir_dest but the next commit gets rid of that so this avoids unnecessary
churn.  Most of this commit was generated by sed:

   sed -i -e 's/dest.dest.ssa/def/g' src/**/*.h src/**/*.c src/**/*.cpp

There were a few manual fixups required in the nir_legacy.c and
nir_from_ssa.c as nir_legacy_reg and nir_parallel_copy_entry both have a
similar pattern.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
 2023-08-14 21:22:53 +00:00
Faith Ekstrand
977999d836 nir: Get rid of nir_dest_is_divergent() 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
 2023-08-14 21:22:53 +00:00
Yonggang Luo
3e72539dc2 radv: Fixes mingw linkage error undefined reference to `radv_GetCalibratedTimestampsEXT' 
message:
../../src/amd/vulkan/radv_sqtt.c:812: undefined reference to `radv_GetCalibratedTimestampsEXT'

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24664>
 2023-08-14 15:00:56 +08:00
Konstantin Seurer
e2a02f3910 clang-format: Disable formatting by default 
This should make `git clang-format` usable for patches that modify
clang formatted and manually formatted code.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9492
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24645>
 2023-08-13 16:48:49 +02:00
Alyssa Rosenzweig
09d31922de nir: Drop "SSA" from NIR language 
Everything is SSA now.

   sed -e 's/nir_ssa_def/nir_def/g' \
       -e 's/nir_ssa_undef/nir_undef/g' \
       -e 's/nir_ssa_scalar/nir_scalar/g' \
       -e 's/nir_src_rewrite_ssa/nir_src_rewrite/g' \
       -e 's/nir_gather_ssa_types/nir_gather_types/g' \
       -i $(git grep -l nir | grep -v relnotes)

   git mv src/compiler/nir/nir_gather_ssa_types.c \
          src/compiler/nir/nir_gather_types.c

   ninja -C build/ clang-format
   cd src/compiler/nir && find *.c *.h -type f -exec clang-format -i \{} \;

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24585>
 2023-08-12 16:44:41 -04:00
Mike Blumenkrantz
e9a5da2f4b nir: add a filter cb to lower_io_to_scalar 
this is useful for drivers that want to do selective scalarization
of io

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24565>
 2023-08-11 09:02:53 +00:00