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radv: fix 128bpp comp-to-single clears

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We were clearing GB to A, instead of R.

This fixes some red tinting in Overwatch 2 when shadow quality is set to
"Ultra".

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 7451eb1d61 ("radv: implement DCC fast clears with comp-to-single")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9446
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24400>
This commit is contained in:
Rhys Perry 2023-07-28 18:09:33 +01:00 • committed by Marge Bot
parent 405f3bf990
commit e2c7ce3719
1 changed files with 7 additions and 5 deletions
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12
src/amd/vulkan/meta/radv_meta_clear.c
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@ -922,10 +922,10 @@ build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa)
output_img->data.binding = 0;
/* Load the clear color values. */
nir_def *clear_values = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 8);
nir_def *clear_values = nir_load_push_constant(&b, 4, 32, nir_imm_int(&b, 8), .range = 24);
nir_def *data = nir_vec4(&b, nir_channel(&b, clear_values, 0), nir_channel(&b, clear_values, 1),
nir_channel(&b, clear_values, 1), nir_channel(&b, clear_values, 1));
nir_channel(&b, clear_values, 2), nir_channel(&b, clear_values, 3));
/* Store the clear color values. */
nir_def *sample_id = is_msaa ? nir_imm_int(&b, 0) : nir_undef(&b, 1, 32);
@ -994,7 +994,7 @@ init_meta_clear_dcc_comp_to_single_state(struct radv_device *device)
&(VkPushConstantRange){
VK_SHADER_STAGE_COMPUTE_BIT,
0,
16,
24,
},
};
@ -1303,15 +1303,17 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, struct radv_im
unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width);
unsigned dcc_height = DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height);
const unsigned constants[4] = {
const unsigned constants[6] = {
image->planes[0].surface.u.gfx9.color.dcc_block_width,
image->planes[0].surface.u.gfx9.color.dcc_block_height,
color_values[0],
color_values[bytes_per_pixel == 16 ? 0 : 1],
color_values[bytes_per_pixel == 16 ? 0 : 1],
color_values[1],
};
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.clear_dcc_comp_to_single_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, constants);
VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, constants);
radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, layer_count);