Commit graph

170456 commits

Author SHA1 Message Date
Thong Thai
27eafdcbd5 util: check and initialize locale before using it
Cc: mesa-stable

Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>
2023-04-27 15:43:33 +00:00
Thong Thai
7373f25c09 mesa/main: rework locale setup/teardown
Cc: mesa-stable

Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>
2023-04-27 15:43:33 +00:00
Ruijing Dong
306c6e12a5 frontends/va: define va av1 encoding caps
by having va av1 caps enabled, av1 vaapi encoding
is enabled.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
03c9a81959 radeonsi/vcn: use PIPE_ENC_FEATURE enum
Merge PIPE_H265_ENC_FEATURE into PIPE_ENC_FEATURE enum
because those are common flags, and it will be
used in AV1 encoder as well.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
5edbecb856 frontends/va: adding va av1 encoding functions
supported features:
- 8/10 bit encoding
- multi-layer (up to 4) encoding
- vbr/cbr rate control mode

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
35c2150988 radeonsi/vcn: add av1 encoding ib packages and get_info
add av1 encoding ib packages and enable the
get_info functions.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
4697b71c4e radeonsi/vcn: add some av1 encoding function
preparation for enabling av1 encoding in radeonsi,
adding the entropy related functioin.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
8b3295b9ed radeonsi/vcn: add av1 enc data structure
add av1 encoding related data structure.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
0b31c5a00c gallium/pipe: add av1 encoding data structure in pipe
add pipe av1 encoding data structure

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
f33f26e9ff radeonsi/vcn: add av1 dpb variables and cdf table
add av1 dpb variables and cdf table.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
b13f87031f radeonsi/vcn: remove extra zero bytes from bitstream
reason:
   extra bytes are not needed and not necessary
   in h264/h265 bitstreams, because they are in
   between NALs, the only problem is they consumed
   extra bits. And for av1 streams, that could be
   explained to something else, especially in
   multi-layer cases, that can cause syntax errors.

   ptr[6] represents the bitstream size,
   ptr[8] represents the extra zero bytes.

   The total number of bytes of the output
   should be ptr[6] - ptr[8]

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
bb08f061d9 radeonsi/vcn: merge get_output_format_param function
reason:
so far, the output_format_param function can be shared
by different encoders, and just for h264 encoder, there
is no 10bit encoding supported. This is to reduce
the repeated code before having av1 encoder.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
a4f96446fb radeonsi/vcn: enable swizzle mode in encoding ref frames.
swizzle mode in ref frames could potentially
improve encoding performance, the main reason
is just because linear mapping is the worst mode
for reference frames comparing to block level
mapping.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
0a11d5f598 radeonsi/vcn: enable 2 pass search center map
2 pass search map is a feature supported by VCN,
the main purpose is to enlarge motion search
range that in pre-encoding path the center global
motion vectors could be obtained and used in the
final path as a block center base. When 2pass is
used, this feature will be automatically enabled.

2 pass feature can be enabled by ffmpeg command
line "-compression_level 1"

and also correct some typos and move quality
package from vcn3.0 to vcn2.0 since it is availabe
in vcn2.0 and vcn3.0 can use it directly. Correct
vcn3.0 hevc spec misc IB package.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Ruijing Dong
869c34c1ca radeonsi/vcn: add macros used in av1 encoding
add macros used in av1 encoding.

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
2023-04-27 15:11:35 +00:00
Rhys Perry
d0caa50dcd aco: don't move exec writes around exec writes
Not sure if this is possible, but we should avoid it anyway.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22714>
2023-04-27 14:33:53 +00:00
José Roberto de Souza
65265d3e32 anv: Take into consideration physical device max heap size to set maxStorageBufferRange
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22721>
2023-04-27 14:05:42 +00:00
David Heidelberg
7508f4b4b6 pvr: drop unused variable
Fixes: 71fe789d35 ("pvr: Support ipf_creq_pf in pvr_isp_ctrl_stream()")

Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22709>
2023-04-27 12:45:52 +00:00
Pierre-Eric Pelloux-Prayer
49cc6edf84 mesa: remove unused bools
ShareGroupReset and DisjointOperation where only set in the code
removed in the previous commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>
2023-04-27 12:06:08 +00:00
Pierre-Eric Pelloux-Prayer
71c5db5e11 mesa: don't share reset status across contexts
If Driver.GetGraphicsResetStatus exists for one context, other contexts
will be able to use it; so there's no need to inherit reset status from
the other contexts.

This also prevented implementing the spec correctly: we're supposed to
report GL_NO_ERROR when the reset is completed (after reporting GL_*_RESET
at least once):

    If a reset status other than NO_ERROR is returned and subsequent
    calls return NO_ERROR, the context reset was encountered and
    completed. If a reset status is repeatedly returned, the context may
    be in the process of resetting.

With the existing code, the contexts will report INNOCENT_CONTEXT_RESET
forever.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>
2023-04-27 12:06:08 +00:00
Pierre-Eric Pelloux-Prayer
b4a2cb1e16 winsys/amdgpu: use the no-op helper to detect if reset completion
On older kernel the completion of the reset isn't signalled to userspace,
yet we need it to implement the EXT_robustness extension correctly.

In this situation, try to create a new context and submit a no-op job. If
the reset isn't done the kernel will reject the submission (-ECANCELED);
otherwise the submission will go through and we'll know that the reset is
done.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>
2023-04-27 12:06:08 +00:00
Pierre-Eric Pelloux-Prayer
45cd75cdad winsys/amdgpu: add a helper function to submit a no-op job
This will be used in the next commit.

Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>
2023-04-27 12:06:08 +00:00
Pierre-Eric Pelloux-Prayer
e528823400 radeonsi: stop reporting reset to app once gpu recovery is done
This way apps know they can recreate their contexts when
the status go back to NO_ERROR.

This depends on new UAPI in the kernel; for older kernel, radeonsi
will stop reporting a reset after 3 seconds. Apps will be able to
create new contexts but they'll have to handle not being able to
submit tasks.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7460
Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>
2023-04-27 12:06:08 +00:00
Pierre-Eric Pelloux-Prayer
5022531120 amd: update amdgpu_drm.h
Reviewed-by: André Almeida <andrealmeid@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290>
2023-04-27 12:06:08 +00:00
Samuel Pitoiset
e996599ed0 ac/rgp: update SQTT_FILE_CHUNK_TYPE_ASIC_INFO to minor version 5
To match PAL. I don't know what the active_pixel_packer_mask field
is used for.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>
2023-04-27 11:31:49 +00:00
Samuel Pitoiset
dd91faaddc ac/rgp: update SQTT_FILE_CHUNK_TYPE_API_INFO to minor version 2
To match PAL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>
2023-04-27 11:31:49 +00:00
Samuel Pitoiset
4cbb0f7ec3 ac/sqtt: add missing EventUnknown to rgp_sqtt_marker_event_type
To match XGL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>
2023-04-27 11:31:49 +00:00
Samuel Pitoiset
637a6813db ac/sqtt: add new bits to rgp_sqtt_marker_barrier_end
To match XGL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22677>
2023-04-27 11:31:49 +00:00
Samuel Pitoiset
930e77e903 radv/sqtt: add support for queue info
RGP uses that to report the various queue timings info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>
2023-04-27 10:55:55 +00:00
Samuel Pitoiset
84a0ef7a33 radv/sqtt: sample CPU/GPU clocks before starting the trace
RGP seems to use that to calibrate timestamps. This also introduces
a new helper to reset thread data between captures.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>
2023-04-27 10:55:55 +00:00
Samuel Pitoiset
ee93864117 ac/sqtt: initialize clock calibration/queue info/queue event records
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>
2023-04-27 10:55:55 +00:00
Samuel Pitoiset
94ce6540d8 ac/sqtt: add helpers for initializing ac_thread_trace_data
This is common between RADV and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>
2023-04-27 10:55:55 +00:00
Samuel Pitoiset
23f3aa3491 ac/sqtt: add a helper for adding clock calibration records
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22594>
2023-04-27 10:55:55 +00:00
Jose Fonseca
16f3e9cd76 wgl: Remove needless if (1) { ... }.
Noticed by Craig Scott on https://gitlab.freedesktop.org/mesa/mesa/-/issues/4427#note_857876

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22706>
2023-04-27 09:58:39 +00:00
Jose Fonseca
9105e771af wgl: Fix unintentional assignment on assert.
Spotted by Nanley Chery.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4427
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22706>
2023-04-27 09:58:39 +00:00
Lionel Landwerlin
5f43f866a2 anv: enable shaderUniformBufferArrayNonUniformIndexing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
2023-04-27 09:08:03 +00:00
Lionel Landwerlin
9fb9ae5ac6 anv: fix anv_nir_lower_ubo_loads pass
In order to use load_global_const_block_intel we need to ensure the
64bit address in src[0] is uniform. This is not the case in the
vkd3d-proton test_bindless_cbv tests for example.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
2023-04-27 09:08:03 +00:00
Lionel Landwerlin
d6e9479d4b nir/divergence: add missing load_global_constant_* intrinsics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
2023-04-27 09:08:03 +00:00
Iago Toral Quiroga
0468ce3791 broadcom/compiler: try harder to merge thread switch earlier
We have been stopping as soon as we find a conflict but that doesn't
mean we can't merge it in an earlier slot, so keep going. Going by
shader-db, this sometimes allows us to merge the final thrsw a bit
earlier and avoid emitting NOP instructions at the program end to
make up for its delay slots. I have not observed cases where this
helps with regular thrsw though, but it doesn't hurt to try with
those too.

total instructions in shared programs: 11526876 -> 11526354 (<.01%)
instructions in affected programs: 10760 -> 10238 (-4.85%)
helped: 236
HURT: 0
Instructions are helped.

total max-temps in shared programs: 2231705 -> 2231677 (<.01%)
max-temps in affected programs: 276 -> 248 (-10.14%)
helped: 27
HURT: 0
Max-temps are helped.

total inst-and-stalls in shared programs: 11545177 -> 11544655 (<.01%)
inst-and-stalls in affected programs: 10777 -> 10255 (-4.84%)
helped: 236
HURT: 0
Inst-and-stalls are helped.

total nops in shared programs: 321624 -> 321152 (-0.15%)
nops in affected programs: 751 -> 279 (-62.85%)
helped: 236
HURT: 0
Nops are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22679>
2023-04-27 08:43:29 +00:00
Gregory Mitrano
13f258fae3 radv/sqtt: Add RGP Markers for Mesh Shaders
This change updates the sqtt layer to add mesh shader specific RGP
instrumentation logic. This should allow RGP to correctly identify GPU
work derived from vkCmdDrawMeshTasksEXT, vkCmdDrawMeshTasksIndirectEXT,
and vkCmdDrawMeshTasksIndirectCountEXT API calls.

This change also updates the mesa-to-RGP shader stage translation logic
to handle the mesh & task stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21917>
2023-04-27 07:58:58 +00:00
Gregory Mitrano
01b7371bb4 ac/sqtt: Add RGP Definitions for Mesh Shaders
This commit adds RGP marker definitions for the following mesh shader
functions:

- vkCmdDrawMeshTasksEXT
- vkCmdDrawMeshTasksIndirectCountEXT
- vkCmdDrawMeshTasksIndirectEXT

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21917>
2023-04-27 07:58:58 +00:00
Samuel Pitoiset
f2d5b7cd1c ac/spm: rename ac_spm_trace_data to ac_spm
This is shorter and it's the main struct that controls SPM, while
ac_spm_trace contains the generated data only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22707>
2023-04-27 07:24:54 +00:00
Samuel Pitoiset
0d4fa8e5c6 ac/spm: introduce ac_spm_trace and ac_spm_get_trace()
For more code isolation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22707>
2023-04-27 07:24:54 +00:00
Samuel Pitoiset
44a2e5ba38 radv: only enable extendedDynamicState3ConservativeRasterizationMode on GFX9+
If extendedDynamicState3ConservativeRasterizationMode is enabled,
VK_EXT_conservative_rasterization is mandatory.

Fixes recent updates in dEQP-VK.info.device_mandatory_features.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22681>
2023-04-27 06:15:16 +00:00
Erik Faye-Lund
0a718c9354 nir: clean up white-space in deref-printing
Without this, we get some trailing spaces in some cases, and some
double space in some other cases. Let's clean that up a bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22550>
2023-04-27 05:39:57 +00:00
Dave Airlie
d8f3060bd9 radv/video: start adding gfx11 vcn decoder
On gfx11 the vcn decoder moved into the vcn encoder ring,
now known as the unified vcn ring.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>
2023-04-27 02:00:03 +00:00
Dave Airlie
89df5976f8 radv/video: fix dpb surface programming
This just programs the dpb fields directly from the image surface.

Makes things happier on navi33

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>
2023-04-27 02:00:03 +00:00
Dave Airlie
6b75c365a8 radv/video: add a video addr gfx mode
This will be different on gfx11+ so add a settable field for it

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>
2023-04-27 02:00:03 +00:00
Dave Airlie
ca7a2e508d radv/winsys: handle encoder queue padding/submits.
The encoder queue doesn't like padding at all, don't pad in the sysmem
paths for encoder queue.

The encoder queue will be using on gfx11 for decoding.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>
2023-04-27 02:00:03 +00:00
Dave Airlie
2fdf75dadf radv: set a video decode ip block in physical device.
This makes it easier to add navi 3x

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21980>
2023-04-27 02:00:03 +00:00