Having one buffer object for input kernel arguments coming from clover
and an other one for OpenGL user uniforms is unnecessary. Using the
uniform_bo object for both GL/CL uniforms avoids to declare a new BO.
This only affects compute programs but it should not hurt anything
because the states are dirtied and data will get reuploaded.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Enlarge the buffer hashlist to prevent large numbers of misses
due to adding more buffers than can be cached in the hashlist.
Ported from winsys/amdgpu: 6373845d98
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Changes:
- don't flush DB for fast color clears
- don't flush any caches for initial clears
- remove the flag from si_copy_buffer, always assume shader coherency
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ideally we'd have nir.h being included with -Wpedantic too, but it fails
with:
src/compiler/nir/nir.h:754:20: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic]
nir_alu_src src[];
^
In file included from src/compiler/nir/glsl_to_nir.cpp:42:0:
src/compiler/nir/nir.h:919:16: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic]
nir_src src[];
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
As they are not standard C++ and are not supported by MSVC C++ compiler.
Just have nir_imm_double match nir_imm_float above.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
The old comment was a bit terse. Also, change the function return
type to bool.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Some hardware (i965 on Broadwell generation, for example) does not support
natively the execution of lrp instruction with double arguments.
Add 'lower_flrp64' flag to lower this instruction in that case.
v2:
- Rename lower_flrp_double to lower_flrp64 (Jason)
- Fix typo (Jason)
- Adapt the code to define bit_size information in the opcodes.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
A later patch will add lower_flrp64 option to NIR.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
At least i965 hardware does not have native support for ceil on doubles.
v2 (Sam):
- Improve the lowering pass to remove one bcsel (Jason).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
At least i965 hardware does not have native support for floor on doubles.
v2 (Sam):
- Improve the lowering pass to remove one bcsel (Jason)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
At least i965 hardware does not have native support for truncating doubles.
v2:
- Simplified the implementation significantly.
- Fixed the else branch, that was not doing what we wanted.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
v2: Move to compiler/nir (Iago)
v3: Use nir_imm_int() to load the constants (Sam)
v4 (Sam):
- Undo line-wrap (Jason).
- Fix comment (Jason).
- Improve generated code for get_signed_inf() function (Connor).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
v2:
- Group num_components and bit_size together (Jason)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
