Commit graph

224128 commits

Author SHA1 Message Date
Calder Young
249c227fa4 anv: Add function to get the list of page faults
Adds function to get the list of page faults, returns NULL if the KMD
is too old or if there was an error retrieving the data.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41318>
2026-06-11 02:44:58 +00:00
Calder Young
39a0d76f64 intel: Add common utils for page fault reporting
Adds some data types and functions for getting the list of page faults
from the KMD using the intel common library.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41318>
2026-06-11 02:44:57 +00:00
Calder Young
5074524788 anv: Track more error codes from certain IOCTLs
The KMDs don't give us a way to query most failure types, we have to track
the error code that was returned by the failing IOCTL to figure out when we
have a PXP invalidation or if the device got disconnected.

These hooks will also give us a place to make the driver to automatically
dump some details about a lost device to the console (such as page fault
addresses) for more visibility to developers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41318>
2026-06-11 02:44:57 +00:00
nyanmisaka
9dfa65db44 intel/dev: update PTL device names
Ref: https://www.intel.com/content/www/us/en/products/sku/245531/intel-core-ultra-5-processor-338h-18m-cache-up-to-4-70-ghz/specifications.html
Ref: https://www.intel.com/content/www/us/en/products/sku/245523/intel-core-ultra-x7-processor-368h-18m-cache-up-to-5-00-ghz/specifications.html

Fixes: efa7aa4e ("intel/dev: Add PTL PCI IDs (with FORCE_PROBE set)")
Fixes: d84d7b78 ("intel/dev: Add PTL PCI IDs 0xb084-0xb087")
Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39931>
2026-06-11 01:02:57 +00:00
Faith Ekstrand
3ebe2b61e8 nvk: Advertise VK_NV_shader_atomic_float16_vector
Some checks are pending
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Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:36 +00:00
Faith Ekstrand
a3fcccb47b nak/from_nir: Handle f16v2 atomics
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:36 +00:00
Faith Ekstrand
b1fe47e944 nak: Rename AtomType::F16x2 to F16v2
This is more consistent with the SrcType.

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:36 +00:00
Sid Pranjale
0e7eda7f23 nak/nir: lower f16vec2 shared atomics
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:35 +00:00
Faith Ekstrand
1a58186ef5 nak/nir: Lower f16vec4 atomics to 2xf16v2
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:35 +00:00
Faith Ekstrand
112d5521e5 spirv,nir: Add support for AtomicFloat16VectorNV
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:34 +00:00
Faith Ekstrand
c6a98cb2d0 nir: Allow atomic intrinsics to have multiple components
v2 (Sid): Handle image and ssbo atomics having only one component in
          ir3, glsl, pco, and zink

Co-authored-by: Sid Pranjale <sidpranjale127@protonmail.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37888>
2026-06-11 00:23:34 +00:00
Nanley Chery
28aba5fba4 anv: Set TRANSFER_DST_BIT for HiZ operations
VK_IMAGE_USAGE_TRANSFER_DST_BIT is needed to recognize a surface as a
destination in get_blorp_surf_for_anv_image(). Set this image usage for
HiZ operations to correct the MOCS programming on gfx12.0.

Fixes: 08e82b28e8 ("anv: use the correct MOCS for depth destinations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42122>
2026-06-10 23:23:59 +00:00
José Roberto de Souza
56d7d5522c anv: Replace va.scratch_surface_state_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:20 +00:00
José Roberto de Souza
c58b2f0d40 anv: Replace va.binding_table_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:20 +00:00
José Roberto de Souza
8a563ad905 anv: Replace va.aux_tt_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:19 +00:00
José Roberto de Souza
1b32e33c01 anv: Replace va.push_descriptor_buffer_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:19 +00:00
José Roberto de Souza
31377140f9 anv: Replace va.indirect_push_descriptor_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:18 +00:00
José Roberto de Souza
f6c0ef6a26 anv: Replace va.dynamic_state_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:17 +00:00
José Roberto de Souza
f745f87711 anv: Replace va.internal_surface_state_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:16 +00:00
José Roberto de Souza
1c3ed6d5bf anv: Replace va.dynamic_visible_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:16 +00:00
José Roberto de Souza
1ffdbe276d anv: Replace va.indirect_descriptor_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:15 +00:00
José Roberto de Souza
ad18acf2f4 anv: Replace va.bindless_surface_state_pool access with a function
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:14 +00:00
José Roberto de Souza
224c60e9ab anv: Use anv_device_get_push_descriptor_buffer_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:14 +00:00
José Roberto de Souza
7e0d7d2609 anv: Use anv_device_get_indirect_push_descriptor_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:13 +00:00
José Roberto de Souza
9ef38baad8 anv: Use anv_device_get_bindless_surface_state_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:13 +00:00
José Roberto de Souza
9713a94ca3 anv: Use anv_device_get_internal_surface_state_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:12 +00:00
José Roberto de Souza
ce49340a13 anv: Use anv_device_get_scratch_surface_state_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:12 +00:00
José Roberto de Souza
0c061693d9 anv: Use anv_device_get_binding_table_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:11 +00:00
José Roberto de Souza
eaf4ec54f4 anv: Use anv_device_get_dynamic_state_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:11 +00:00
José Roberto de Souza
dfa0f7a26a anv: Use anv_device_get_aux_tt_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:10 +00:00
José Roberto de Souza
dbf64e9ad5 anv: Use anv_device_get_general_state_pool()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:10 +00:00
José Roberto de Souza
9d06679d89 anv: Add function to get each anv_state_pool
Xe3P will allow us to reduce the number of anv_state_pool in use, this will
improve performance as it will result in less uAPI calls to allocate memory
and less memory waste in anv_state_pool with not much use.

As this will be a run-time decision, here I'm adding a function to get each
anv_state_pool, then we can just change the function and all the callers will
use the correct anv_state_pool.

Next patches will replace directly access to each anv_state_pool by
a function call in the next patches.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42133>
2026-06-10 22:49:10 +00:00
Julien Schueller
fd616bab71 glx: avoid crash on glXBindTexImageEXT when no texture target set
Some checks are pending
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If a GLXPixmap is created without GLX_TEXTURE_TARGET_EXT,
textureTarget remains 0. Calling glXBindTexImageEXT on such a
drawable would pass 0 to _mesa_get_current_tex_object(), triggering
an internal implementation error and a null-pointer segfault.

Return early when textureTarget is 0 - the drawable was never set
up for texturing, so bind is a no-op.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Assisted-by: DeepSeek V4 Flash
Closes: #58
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42093>
2026-06-10 20:57:35 +00:00
Benjamin Cheng
69c7f6d456 radv/video: Use {min,max}_qp caps from ac
Some checks are pending
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Signed-off-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42136>
2026-06-10 20:34:33 +00:00
Benjamin Cheng
880fbcbeee ac/video: Add {min,max}_qp to video enc caps
Signed-off-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42136>
2026-06-10 20:34:33 +00:00
Benjamin Cheng
c2e76e111d radv/video: Report MULTIPLE_SLICE_SEGMENTS_PER_TILE_BIT
VCN supports one tile only, but with multiple slice segments.

Cc: mesa-stable
Signed-off-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42136>
2026-06-10 20:34:33 +00:00
Benjamin Cheng
b8b8035c6b radv/video: Set accurate minQp/QIndex
The spec requires us to follow the constantQp/base_q_idx from the app,
which is constrained by the caps. Report the more accurate caps.

Cc: mesa-stable
Signed-off-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42136>
2026-06-10 20:34:33 +00:00
Job Noorman
11334c438a ir3: fix possible signed overflow in ir3_link_add
`1 << 31` is undefined since `1` is a signed integer.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 1f9839907a ("ir3: Skip missing VS outputs in VS out map when linking")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42147>
2026-06-10 20:07:01 +00:00
Christian Gmeiner
b83f446642 panvk: Advertise VK_KHR_shader_fma
vtn lowers OpFmaKHR to nir_op_ffma and every Mali has a native fused
multiply-add, so there is nothing to do in the backend.

fp16 is gated on shaderFloat16. A 16-bit OpFmaKHR also needs the Float16
capability and only shaderFloat16 turns that on, so without it the bit
would not be usable. Mali has no fp64, so that one stays off.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42075>
2026-06-10 19:42:49 +00:00
Danylo Piliaiev
67471fed86 tu: Enable texel buffer / SSBO emulation for known problematic games
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Job Noorman
9b32234726 tu: Add option to raise the maximum SSBO size
Emulates SSBOS via global memory, real SSBO size and global base address
are stored in the descriptor. The size can be accessed using resbase,
the base address is parsed manualy from the descriptor by passing the
bindless base address into the shader via a driver UBO or const file.

nir_lower_ssbo is used to lower SSBO accesses to global memory when the
buffer size exceeds the limit. We also use it to insert bounds checks on
global memory. The final code for SSBO accesses looks like this:

if (@get_ssbo_size >= max_storage_buffer_range_bytes) {
    if (offset < @get_ssbo_size) {
        // global memory access using base (from resbase) + offset
    } else {
        // do nothing (stores) or return 0 (loads)
    }
} else {
    // original SSBO access
}

A new pass is added to lower @load_ssbo_address generated by
nir_lower_ssbo. We set native_offset=true for nir_lower_ssbo to make
sure it doesn't generate 64 bit address math. The new pass then
transforms @load/store_global into @load/store_global_ir3 passing the 32
bit offset from @load_ssbo_address.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Co-authored-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Danylo Piliaiev
dc1bb7bbf4 tu: Add option to raise the maximum texel buffer size
Emulates texel buffers via 3D image access, real texel buffer
size and start offset (due to image aligment requirements) are
stored in the descriptor and accessed via resbase.

- Read-only access: isam.a.1d to read as 3d image.
- RW access: stib.b.typed.3d/ldib.b.typed.3d to read as 3d image.

Verified that proprietary D3D12 driver uses the same workaround,
the only difference is that proprietary driver uses arrayed 2d load
for read-only access instead of 3d load, but benefits are not verified.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Danylo Piliaiev
652864e385 tu/a8xx: Set real storage/texel buffer size limits
From tests A8XX seem to fix incompatible with D3D12 limits.
However, proprietary driver exposes old texel buffer element limit.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Danylo Piliaiev
d18b637a7c tu: Specify max texel buffer and storage buffer limits via GPU props
A8XX has different storage buffer range limit.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Danylo Piliaiev
fd99d813af tu: Add allow_oob_indirect_ubo_loads to device cache uuid
Fixes: f4c40fc89c ("tu: Add workaround for D3D11 games accessing UBO out of bounds")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Danylo Piliaiev
3c36e3b7b1 ir3: Add resbase_ir3 intrinsic
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Job Noorman
2fee7ac87f nir/lower_ssbo: add option to insert bounds checks
This is mostly useful in combination with `min_ssbo_size` when the
native SSBO access instructions do the bounds check in HW so we don't
want to add bounds checks for all SSBO accesses.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Job Noorman
7b2dfdf15d nir/lower_ssbo: add option to only lower large SSBOs
Some HW may have native SSBO instructions that only support a limited
buffer size. It may be beneficial to use those instructions for small
SSBOs and only fall back to global memory accesses for large ones.

This commit adds an option (min_ssbo_size) that, if non-zero, will cause
code like this to be emitted:

if (@get_ssbo_size >= min_ssbo_size) {
    // global memory access
} else {
    // original SSBO access
}

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Job Noorman
ca9c01ddc5 nir/lower_ssbo: take offset_shift into account
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00
Job Noorman
c0c1a2b0af nir/get_io_index_src_number: support @load_ssbo_address
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41477>
2026-06-10 18:15:01 +00:00