Commit graph

14137 commits

Author SHA1 Message Date
Emma Anholt
241bc5da70 intel/elk: Use the pixel_coord UW x/y values for noncoherent FB reads.
No need to force generating the float cast just to turn it back to an int.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:39 +00:00
Emma Anholt
1134cdc198 intel/elk: Lower load_frag_coord to load_{pixel_coord,frag_coord_z/w} in NIR.
This moves some conversions to NIR that may get eliminated, and also
distinguishes gl_FragCoord.z/w loads at the shader info level so we don't
need to flag uses_src_depth/uses_src_w when only gl_FragCoord.xy get used
(as is typical).  This reduces thread payload setup on many shaders.
Also, interestingly, blorp shaders stop reserving space for z/w despite
not putting them in the payload (since PS_EXTRA isn't filled out for z/w).

HSW shader-db is noise:

total instructions in shared programs: 9942649 -> 9942997 (<.01%)
instructions in affected programs: 143167 -> 143515 (0.24%)

total cycles in shared programs: 314768862 -> 314299112 (-0.15%)
cycles in affected programs: 62951452 -> 62481702 (-0.75%)

LOST:   44
GAINED: 26

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:39 +00:00
Emma Anholt
88f1656133 intel/elk: Save the UW pixel x/y as a temp.
This will be used for representing gl_FragCoord in NIR and reducing
payload registers pushed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:38 +00:00
Emma Anholt
5222c35924 intel/elk: Save the UW pixel x/y as a temp on gfx6+.
This will be used for representing gl_FragCoord in NIR and reducing
payload registers pushed.

HSW results:

total instructions in shared programs: 9940636 -> 9948574 (0.08%)
instructions in affected programs: 852560 -> 860498 (0.93%)

total cycles in shared programs: 314804525 -> 314900080 (0.03%)
cycles in affected programs: 39786599 -> 39882154 (0.24%)

LOST:   5
GAINED: 11
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:38 +00:00
Emma Anholt
af74abd68c intel/fs: Don't bother checking if load_frag_coord uses interpolation.
This was leftover dead code from 4bb6e6817e ("intel: Use a system value
for gl_FragCoord") -- the sysval doesn't do any interpolation and doesn't
have sources that could use a barycentric.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:37 +00:00
Emma Anholt
1b9b63de37 intel/shim: Report I915_PARAM_HAS_GEN7_SOL_RESET.
Quiets more startup warnings from drm-shim.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:37 +00:00
Emma Anholt
1b6689d79e intel/shim: Report support for PXP status.
Otherwise drm-shim complains on every shader-db run.

Fixes: e358173fbf ("iris: Add GET_PARAM for protected context capability support")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25190>
2025-06-18 23:11:37 +00:00
Emma Anholt
0bf114736a intel: Use the common NIR lowering for fquantize2f16.
This generates one extra instruction to set the rounding mode to RTE due
to f2f16_rtne in the lowering.  This changes the result for
fquantize2f16(65505.0) from 65536 to 65504, which fixes SPIR-V
conformance for this value:

    If Value is positive with a magnitude too large to represent as a
    16-bit floating-point value, the result is positive infinity. If Value
    is negative with a magnitude too large to represent as a 16-bit
    floating-point value, the result is negative infinity.

SPIR-V doesn't specify whether this overflow check is before or after
rounding, but IEEE specifies rounding first, which is what produces our
65504.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25552>
2025-06-18 22:45:08 +00:00
Yiwei Zhang
4efaa64159 vulkan/treewide: add and use common Android HMI hal implementation
There's no need for a per driver HMI implementation since the
vk_icdGetInstanceProcAddr implementation can well populate the required
entrypoints for Android icd.

Changes have to be done in this single commit for simplicity. Otherwise,
I would have to create a separate android shared library in the runtime
like how vk_instance is handled today, so that the target is able to
check per driver enablement def. However, after all drivers have
migrated over within this MR, we still have to clean those up. So I
decided to just do those in a single commit instead.

v2: avoid preloading u_gralloc in vulkan hal open

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
2025-06-18 22:23:53 +00:00
Yiwei Zhang
02c65181c1 hasvk: free up hwvulkan_device_t upon driver unloading
Per <hardware/hwvulkan.h>, the hw_device_t::close() function is called
upon driver unloading. The behavior has been like this since Android 10.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
2025-06-18 22:23:49 +00:00
Yiwei Zhang
710282f83c anv: adopt common Android gralloc helpers
u_gralloc will be initialized upon the initial vk_android_get_ugralloc.

v2: drop explicit gralloc init

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
2025-06-18 22:23:49 +00:00
Yiwei Zhang
896bda5143 anv: free up hwvulkan_device_t upon driver unloading
Per <hardware/hwvulkan.h>, the hw_device_t::close() function is called
upon driver unloading. The behavior has been like this since Android 10.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35561>
2025-06-18 22:23:49 +00:00
Sagar Ghuge
a676ba9294 anv: Apply flush during WriteAccelerationStructures
We are reading accel header parameter those are updated by CS, so we
need to apply flushes to make L3 coherent with CS.

This fixes ray query tests on MTL:
- dEQP-VK.ray_query.*.serialization.*

Cc: mesa-stable

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35590>
2025-06-18 20:56:56 +00:00
José Roberto de Souza
37f4182ac3 Revert "anv: Enable preemption due 3DPRIMITIVE in GFX 12"
Enabling preemption in 3DPRIMITIVE is causing glitches on Dota 2,
so reverting this until the issue with preemption is fixed.

This reverts commit 3cd972a2d3.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13289
Fixes: 12ddaa6b8b ("anv: Enable preemption due 3DPRIMITIVE in GFX 12")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35586>
2025-06-18 18:52:19 +00:00
Valentine Burley
e82e1bca1d intel/ci: Drop deprecated fp16 environment variable
Fixes: cf3ec8d3b9 ("rusticl: enable proper fp16 support")
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35574>
2025-06-18 06:13:25 +00:00
Valentine Burley
04d35cacbf intel/ci: Reduce parallelism of intel-adl-cl job
The intel-adl-cl job was previously running on two DUTs, but the
runtime reported by deqp-runner was only about 3 minutes.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35574>
2025-06-18 06:13:25 +00:00
Valentine Burley
68244ee819 anv/ci: Add a pre-merge vkd3d job on ADL
Introduce a new, pre-merge vkd3d-proton job on Alder Lake, and move the
VK_DRIVER variables to the .anv-test template.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35574>
2025-06-18 06:13:25 +00:00
Yiwei Zhang
5cb50c3cf5 hasvk: use narrow range to match up with mesa EGL
This matches up with the native gl drivers as well as the media stack.

- VK_SAMPLER_YCBCR_RANGE_ITU_NARROW <=> EGL_YUV_NARROW_RANGE_EXT

Cc: mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35597>
2025-06-17 22:51:40 -07:00
Yiwei Zhang
c169ad60c1 anv: use narrow range to match up with mesa EGL
This matches up with the native gl drivers as well as the media stack.

- VK_SAMPLER_YCBCR_RANGE_ITU_NARROW <=> EGL_YUV_NARROW_RANGE_EXT

Cc: mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35597>
2025-06-17 22:51:30 -07:00
Calder Young
03cdb3078a anv: Support multi-planar formats in anv_formats_are_compatible
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
2025-06-17 11:23:46 +00:00
Lionel Landwerlin
f4c1753c1a anv: report color/storage features on YCbCr images with EXTENDED_USAGE
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13219
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
2025-06-17 11:23:46 +00:00
Lionel Landwerlin
bd959ea48f anv: pass image usage/flags to anv_get_image_format_features2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
2025-06-17 11:23:46 +00:00
Lionel Landwerlin
befc2a2f62 anv: fix R64 format support reporting
We only want the atomic bit to be conditional to non sparse.

Also take the opportunity to fix buffer features and report the same
supported atomic formats as images.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ed77f67e44 ("anv: add emulated 64bit integer storage support")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35358>
2025-06-17 11:23:45 +00:00
Lionel Landwerlin
4dad9d443b anv: fix valgrind warning
Some checks are pending
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Found when running
KHR-Single-GL46.arrays_of_arrays_gl.InteractionArgumentAliasing2_var_type_index_4
with zink/anv :

Test case 'KHR-Single-GL46.arrays_of_arrays_gl.InteractionArgumentAliasing2_var_type_index_4'..
==22722== Thread 3 glcts:zfq0:
==22722== Uninitialised byte(s) found during client check request
==22722==    at 0x134A8D51: anv_batch_bo_finish (anv_batch_chain.c:350)
==22722==    by 0x134ACD3E: anv_cmd_buffer_end_batch_buffer (anv_batch_chain.c:1114)
==22722==    by 0x13CECB30: end_command_buffer (genX_cmd_buffer.c:3467)
==22722==    by 0x13CECB7B: gfx12_EndCommandBuffer (genX_cmd_buffer.c:3478)
==22722==    by 0x6FFA343: submit_queue (zink_batch.c:739)
==22722==    by 0x672684B: util_queue_thread_func (u_queue.c:294)
==22722==    by 0x6790976: impl_thrd_routine (threads_posix.c:43)
==22722==    by 0x579BAA3: start_thread (pthread_create.c:447)
==22722==    by 0x5828A33: clone (clone.S:100)
==22722==  Address 0x94ac840 is 2,112 bytes inside a block of size 8,192 client-defined
==22722==    at 0x134A04C7: anv_bo_pool_alloc (anv_allocator.c:1311)
==22722==    by 0x134A8772: anv_batch_bo_create (anv_batch_chain.c:262)
==22722==    by 0x134AB6BC: anv_cmd_buffer_init_batch_bo_chain (anv_batch_chain.c:877)
==22722==    by 0x134BCC4C: anv_create_cmd_buffer (anv_cmd_buffer.c:146)
==22722==    by 0x152FEBE4: vk_common_AllocateCommandBuffers (vk_command_pool.c:218)
==22722==    by 0x133FEA1D: vkAllocateCommandBuffers (trampoline.c:1950)
==22722==    by 0x6FF8AE4: create_batch_state (zink_batch.c:367)
==22722==    by 0x6FF91B5: get_batch_state (zink_batch.c:495)
==22722==    by 0x6FF91DB: zink_reset_batch (zink_batch.c:504)
==22722==    by 0x6FF9424: zink_start_batch (zink_batch.c:537)
==22722==    by 0x706C01D: zink_context_create (zink_context.c:5647)
==22722==    by 0x60403A6: st_api_create_context (st_manager.c:978)
==22722==

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d21e7e5a9f ("anv: Query sampler offset in set_image_clear_color()")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35549>
2025-06-16 18:26:30 +00:00
Sagar Ghuge
3696f85b63 anv: Drop unused helper cmd_buffer_dispatch_kernel
Drop some more unused fields: (Lionel)
- kernel_args_size, kernel_arg_count & kernel_args
- anv_kernel_arg
- anv_kernel
- max_grl_scratch_size

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35530>
2025-06-16 15:22:09 +00:00
Lucas Fryzek
49f5cc48cf anv: Add format conversion for AHARDWAREBUFFER_FORMAT_YCbCr_P010
Reviewed-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35161>
2025-06-16 10:52:25 +00:00
Sushma Venkatesh Reddy
03fc7d6a6d intel/perf: Add PTL OA support
Some checks are pending
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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35298>
2025-06-16 09:01:30 +00:00
Derek Foreman
07881b085e vulkan: Enable PresentWait2 on many physical devices
PresentWait2 should be possible on any physical device, as it adds a
surface capability query that depends on common wsi code.

Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35414>
2025-06-13 15:52:02 +00:00
Hyunjun Ko
0d3ffd8275 anv: enable the KHR_video_decode_vp9 extension
Some checks are pending
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Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
2025-06-13 04:51:51 +00:00
Hyunjun Ko
314de7af06 anv: Initial support for VP9 decoding
Helped from: Stéphane Cerveau <scerveau@igalia.com>
- Fix crash when segmentation is unavailable
- Set 8x8 to minCodedExtent
- Fix typo for GOLDEN and ALTREF scale factor

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
2025-06-13 04:51:51 +00:00
Hyunjun Ko
0689e3d873 anv: add default vp9 tables from FFMpeg and intel-vaapi-driver
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
2025-06-13 04:51:51 +00:00
Hyunjun Ko
213ca2ac9a intel/genxml: fix HCP_VP9 commands
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35485>
2025-06-13 04:51:51 +00:00
Lionel Landwerlin
d0608425f4 anv: handle REMAINING_LAYERS with 3D images & maintenance9
Some checks are pending
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9a1485ec5c ("anv: missing bit from maintenance9")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35487>
2025-06-12 11:34:33 +00:00
Tapani Pälli
58c4b31d31 anv: small cleanup, remove unused helper function
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35450>
2025-06-12 11:15:21 +00:00
Lionel Landwerlin
9a1485ec5c anv: missing bit from maintenance9
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 595889018a ("anv: implement VK_KHR_maintenance9")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35467>
2025-06-12 09:14:20 +03:00
Jianxun Zhang
a9aad4565f anv: Enable compression on CCS modifiers (xe2)
Some checks are pending
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Don't report compressed memory type in the case of Xe2 modifiers
as the Vulkan spec requires identical memory types behind the
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT.

Instead, we require dedicated allocation to get the right
compressed memory in allocation stage. The BMG modifier also
requires scanout flag to set. Refer to comments.

Thanks for the help from:
Nanley Chery <nanley.g.chery@intel.com>
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke <kenneth@whitecape.org>
and other people not listed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
2025-06-12 04:07:12 +00:00
Jianxun Zhang
a45143e04c anv: Don't choose compression modifier when aux is disabled
When aux has to be disabled (ISL_SURF_USAGE_DISABLE_AUX_BIT)
for some reasons like VK_SHARING_MODE_CONCURRENT, we simply
cannot implicitly choose any modifier with compression.

Otherwise, we run into a situation that an image is created
with a modifier but without the aux support that modifier
requires. It will fail a CTS test once Xe2 modifiers are
enabled:

dEQP-VK.wsi.wayland.swapchain.private_data.image_sharing_mode

MESA: warning: ../src/intel/vulkan/anv_image.c:1198: image with
modifier unexpectedly has wrong aux usage (VK_ERROR_UNKNOWN)

GFX12.x (MTL) does not show this failure because only one queue
family is present. But they will face the same issue when aux is
disabled for any other reasons:

NotSupported (Only 1 queue families available for
VK_SHARING_MODE_CONCURRENT at vktWsiSwapchainTests.cpp:715)

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
2025-06-12 04:07:12 +00:00
Jianxun Zhang
7c2f340d37 anv: Align size of compressed scanout buffers to 64KB on BMG (xe2)
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
2025-06-12 04:07:11 +00:00
Jianxun Zhang
b7f7f1c74f anv: Treat imported compressed buffers as displayable (xe2)
As a part of the effort to unify the displayable attribute
on dmabuf sharing across drivers, we set scanout flag on
imported bos on Xe2+.

Refer to the comment in the change.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
2025-06-12 04:07:11 +00:00
Jianxun Zhang
2660b7c49d isl: Add Xe2 CCS modifiers (xe2)
Narrow down the definition of two compression flags suggested by
Nanley Chery <nanley.g.chery@intel.com> so that we can address
the unified compression support of Xe2 modifiers and don't have
to set media compression flag thats result more update in the
stack.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34567>
2025-06-12 04:07:10 +00:00
Collabora's Gfx CI Team
350eccd032 Uprev Piglit to a0a27e528f643dfeb785350a1213bfff09681950
685ea49b47...a0a27e528f

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35303>
2025-06-11 21:14:59 +00:00
Lionel Landwerlin
595889018a anv: implement VK_KHR_maintenance9
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35381>
2025-06-11 14:09:56 +00:00
Lionel Landwerlin
884df891d7 anv: allow device creation with no queue
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35381>
2025-06-11 14:09:56 +00:00
Lionel Landwerlin
1d8382b88e brw: enable more lowering for bitfield manipulation at non 32bit sizes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35381>
2025-06-11 14:09:56 +00:00
Daniel Stone
4b2a4dce78 ci: Skip check-only container jobs for pre-merge
For pre-merge pipelines, we know that we don't need to run the
container-check jobs unless image-tags.yml has been modified. In this
case, we can just skip the container jobs, because we 'know' that the
containers are present in the upstream repo.

For downstream or off-main pipelines, we still need to run the check
job, because the changed-file tracking is not reliable on other
branches, and because we may need to copy the container image from the
upstream container storage into the user's namespace.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35203>
2025-06-10 14:37:14 +00:00
Valentine Burley
5ee7a4c1e9 ci: Uprev GL & GLES CTS
Update to the newest releases.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13076
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34321>
2025-06-10 07:56:46 +00:00
Lionel Landwerlin
07c2b90e25 ci: add intel format emulation testing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35383>
2025-06-10 07:16:27 +00:00
Sushma Venkatesh Reddy
a796b4a0d2 intel/tools: Reflect SIMD lane count for EUs in device info output
Update the device info output to display EU count together with the native
SIMD width. This clarifies the SIMD width of execution units and explains
differences in EU counts between hardware generations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35116>
2025-06-10 06:55:27 +00:00
Paulo Zanoni
12192f6489 brw: properly decode TGL_PIPE_SCALAR
Source: BSpec "Instruction Fields" page (56701), SWSB field.

Credits to Caio Oliveira here, since he was helping me while we found
this issue together.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35395>
2025-06-09 22:21:13 +00:00
Nanley Chery
b2ad1333d0 anv: Use genX(set_fast_clear_state)() in transition_depth_buffer()
Simplify transition_depth_buffer() by reusing a function to update the
fast-clear value instead of open-coding that logic.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35329>
2025-06-09 17:40:21 +00:00