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anv: Apply flush during WriteAccelerationStructures

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We are reading accel header parameter those are updated by CS, so we
need to apply flushes to make L3 coherent with CS.

This fixes ray query tests on MTL:
- dEQP-VK.ray_query.*.serialization.*

Cc: mesa-stable

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35590>
This commit is contained in:
Sagar Ghuge 2025-06-17 09:36:04 -07:00 • committed by Marge Bot
parent 6446433761
commit a676ba9294
1 changed files with 11 additions and 4 deletions
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15
src/intel/vulkan/genX_query.c
View file

@ -2066,10 +2066,17 @@ genX(CmdWriteAccelerationStructuresPropertiesKHR)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_END_OF_PIPE_SYNC_BIT |
ANV_PIPE_DATA_CACHE_FLUSH_BIT,
"read BVH data using CS");
/* L1/L2 caches flushes should have been dealt with by pipeline barriers.
* Unfortunately some platforms require L3 flush because CS (reading the
* dispatch parameters) is not L3 coherent.
*/
if (!ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info)) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_END_OF_PIPE_SYNC_BIT |
ANV_PIPE_DATA_CACHE_FLUSH_BIT,
"read BVH data using CS");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
}
if (append_query_clear_flush(
cmd_buffer, pool,