Dynamic renderpasses need vsc_prim_strm_pitch, vsc_draw_strm_pitch
values, and a correct BO. The easiest way to solve this is to
lazily init VSC when it is needed, and not at every cmdbuf
initialization.
Fixes CTS tests (when running with TU_DEBUG=gmem,forcebin):
dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18996>
If enabled, use a scoped trace to see where calls happen on frontend vs
where they are pushed down to driver. This is much lighter weight than
printf based tracing, but would still be an extra few instructions even
if perfetto tracing isn't active, so it is not enabled by default.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
Use the MESA_TRACE_BEGIN/END() macros which will generate perfetto
traces (if perfetto is enabled) otherwise atrace (if android build), in
either case creating track events which will show up on the frontend
thread in a perfetto trace, giving visibility into where syncs happen.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
Fix#7432: unknown nir_op flrp assertion
This copy-pastes src/gallium/drivers/radeonsi/si_shader_nir.c
The lower_flrp16 value differs given chipset >= NVISA_GV100_CHIPSET.
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19003>
A lot of code zero-initializes pipe_sampler_state, and sets the states
the non-zero fields manually. This means that normalized_coords is the
"default" setting.
However, setting normalized_coords to true isn't allways allowed, and
we'd need to check PIPE_CAP_TEXRECT first. So it's not really the ideal
default here. There's recently been found quite a bit of bugs in this
area, where the state-tracker didn't properly lower texrects.
Let's switch this around to avoid more bugs like this in the future.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18971>
Take the opportunity to prune some ftraces that are not that useful
and fill the buffer pretty fast.
Record time is bumped to 1.2s
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18930>
Instead of relying on a certain BVH layout, this patch traverses the BVH
from the root node which gets rid of any layout requirements.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18967>
When called with FD_BO_PREP_FLUSH as the only op bit set, the intention
is to only sync with the submit-queue.. we shouldn't be calling down to
the kernel (where op==0 gets interpreted as MSM_PREP_READ).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
Fixes:
src/gallium/drivers/r600/sfn/sfn_nir.cpp:832: int r600_shader_from_nir(r600_context*, r600_pipe_shader*, r600_shader_key*): Assertion `shader' failed.
karolherbst said:
> long term r600 should implement PIPE_CAP_SHAREABLE_SHADERS
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18963>
Fixes:
thread '<unnamed>' panicked at 'Context missing features. This should never happen!', ../src/gallium/frontends/rusticl/mesa/pipe/context.rs:44:13
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18962>
We're now using PIPE_SHADER_MAX_SAMPLER_VIEWS, so this advice is
outdated.
Fixes: 620c5e9dd0 ("gallium/u_threaded_context: Use PIPE_MAX_SHADER_SAMPLER_VIEWS for sampler_buffers")
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18973>
reallocate the surface appropriately based on the mjpeg sampling factor
v2:
use macros for mjpeg sampling factors (Ruijing Dong)
indentation fix (Thong Thai)
v3:
add comments to mention workaround of reallocation (Boyuan Zhang)
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
v2: set third plane offset only for 3 plane formats (Boyuan Zhang)
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
check if vaprofile supports decode of yuv400 and yuv444 formats
and enable the corresponding rt_formats in vaconfig.
v2: use config->entrypoint as param instead of BITSTREAM (Sil Vilerino)
Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
pvr_cmd_buffer_alloc_mem takes size in bytes. This change
fixes the invocations which assume it to be size in dwords.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Also changing struct pvr_descriptor_program_input to
struct pvr_pds_descriptor_program_input for consistency with
other similar structs defined in pvr_pds.h.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18976>
Failing to allocate resources when DRM_FORMAT_INVALID
is passed as a modifier breaks tegra. Change this behaviour
so that this modifier is instead interpreted as a don't care,
allowing for the driver to choose an appropriate modifier internally.
v2: change nouveau instead of tegra (Thierry Rieding)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6693
Fixes: 129d83cac2 ("nouveau: Use format modifiers in buffer allocation")
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18649>
Since this is no longer needed we can as well free the
memory right away instead of waiting until the parent
shader is freed.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
We don't check whether the register is overwritten between the actual
conditional test and the test of the used result, so don't try to
optimize the evaluation of the conditional.
Fixes: 79ca456b48
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18983>
