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radeonsi/vcn: enable jpeg decode of yuv444 and yuv400

Browse source 
v2: set third plane offset only for 3 plane formats (Boyuan Zhang)

Signed-off-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18914>
This commit is contained in:
James Zhu 2022-09-26 10:06:13 +05:30 • committed by Leo Liu
parent 6b933676cc
commit 3e2f7905a6
3 changed files with 39 additions and 4 deletions
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1
src/amd/common/ac_vcn_dec.h
View file

@ -1154,6 +1154,7 @@ struct jpeg_params {
unsigned dt_uv_pitch;
unsigned dt_luma_top_offset;
unsigned dt_chroma_top_offset;
unsigned dt_chromav_top_offset;
bool direct_reg;
};

30
src/gallium/drivers/radeonsi/radeon_vcn_dec_jpeg.c
View file

@ -40,13 +40,31 @@ static struct pb_buffer *radeon_jpeg_get_decode_param(struct radeon_decoder *dec
struct pipe_picture_desc *picture)
{
struct si_texture *luma = (struct si_texture *)((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma =
(struct si_texture *)((struct vl_video_buffer *)target)->resources[1];
struct si_texture *chroma, *chromav;
dec->jpg.bsd_size = align(dec->bs_size, 128);
dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset;
if (target->buffer_format == PIPE_FORMAT_NV12)
dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
dec->jpg.dt_chroma_top_offset = 0;
dec->jpg.dt_chromav_top_offset = 0;
switch (target->buffer_format) {
case PIPE_FORMAT_IYUV:
case PIPE_FORMAT_YV12:
case PIPE_FORMAT_Y8_U8_V8_444_UNORM:
chromav = (struct si_texture *)((struct vl_video_buffer *)target)->resources[2];
dec->jpg.dt_chromav_top_offset = chromav->surface.u.gfx9.surf_offset;
chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
break;
case PIPE_FORMAT_NV12:
case PIPE_FORMAT_P010:
case PIPE_FORMAT_P016:
chroma = (struct si_texture *)((struct vl_video_buffer*)target)->resources[1];
dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset;
break;
default:
break;
}
dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
dec->jpg.dt_uv_pitch = dec->jpg.dt_pitch / 2;
@ -249,6 +267,10 @@ static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer
set_reg_jpeg(dec, vcnipUVD_JPEG_DATA, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1);
set_reg_jpeg(dec, vcnipUVD_JPEG_DATA, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
if (dec->jpg.dt_chromav_top_offset) {
set_reg_jpeg(dec, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 2);
set_reg_jpeg(dec, vcnipUVD_JPEG_DATA, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
}
set_reg_jpeg(dec, vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0);
// set output buffer read pointer

12
src/gallium/drivers/radeonsi/si_get.c
View file

@ -806,6 +806,8 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
enum pipe_video_profile profile,
enum pipe_video_entrypoint entrypoint)
{
struct si_screen *sscreen = (struct si_screen *)screen;
/* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
@ -815,6 +817,16 @@ static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_for
if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
/* JPEG supports YUV400 and YUV444 */
if (profile == PIPE_VIDEO_PROFILE_JPEG_BASELINE) {
if (sscreen->info.family >= CHIP_NAVI21)
return (format == PIPE_FORMAT_NV12 || format == PIPE_FORMAT_Y8_400_UNORM ||
format == PIPE_FORMAT_Y8_U8_V8_444_UNORM);
else
return (format == PIPE_FORMAT_NV12);
}
/* we can only handle this one with UVD */
if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
return format == PIPE_FORMAT_NV12;