Commit graph

2806 commits

Author SHA1 Message Date
Samuel Pitoiset
54e2470047 radv: fix setting VGT_REUSE_OFF for TES on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 09:54:16 +02:00
Samuel Pitoiset
d2a8b63a2c radv: fix computing the number of ES VGPRS for TES on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 09:54:14 +02:00
Samuel Pitoiset
2974df819e radv: set max workgroup size to 128 for TES as NGG on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 09:54:12 +02:00
Samuel Pitoiset
53c75f17ec radv: fix allocating USER SGPRs on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 09:54:11 +02:00
Bas Nieuwenhuizen
f7f08b2d81 radv/gfx10: Enable tess.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:04:29 +10:00
Bas Nieuwenhuizen
795adbbadd radv/gfx10: Add pipeline state support for tess.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:04:26 +10:00
Bas Nieuwenhuizen
23c6698ea2 radv/gfx10: Only set HW edge flags with gs & tess disabled.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:04:23 +10:00
Bas Nieuwenhuizen
9a8e4a07ad radv/gfx10: Add tess eval ngg shader support.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:04:20 +10:00
Bas Nieuwenhuizen
204e4da9b4 radv: Use correct gs_out with tessellation.
We should use the primitives output by the TES in that case.

There is always a separate TES if there is no GS.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:04:16 +10:00
Bas Nieuwenhuizen
343a435c46 radv/gfx10: Use correct count of max_offchip_buffers.
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:04:12 +10:00
Bas Nieuwenhuizen
5d0dbc2564 radv/gfx10: Load global pointers in correct userdata registers for hs/gs.
Fixes: cfaad5e3ca "radv/gfx10: implement radv_emit_global_shader_pointers()"

Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-09 12:03:51 +10:00
Dave Airlie
6422fa75b4 radv: only use specialised 3D meta paths on GFX9.
GFX10 appears to act like GFX8 here.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-09 06:32:28 +10:00
Samuel Pitoiset
9b116173b6 radv: do not emit VGT_FLUSH on GFX10
We don't need it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-08 14:45:23 +02:00
Connor Abbott
118a66df99 radv: Use NIR barycentric intrinsics
We have to add a few lowering to deal with things that used to be dealt
with inline when creating inputs. We also move the code that fills out
the radv_shader_variant_info struct for linking purposes to
radv_shader.c, as it's no longer tied to the NIR->LLVM lowering.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-08 14:18:25 +02:00
Connor Abbott
27f0c3c15e radv: Make FragCoord a sysval
load_fragcoord is already handled in common code for radeonsi, so we
don't need to do anything to handle it. However, there were some passes
creating NIR with the varying, so we switch them over to the sysval. In
the case of nir_lower_input_attachments which is used by both radv and
anv, we add handling for both until intel switches to using a sysval.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-08 14:14:53 +02:00
Daniel Schürmann
e41e932e57 radv: Lower input attachments in NIR.
v2 (Connor)
- Fix warning in release mode using MAYBE_UNUSED

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-08 14:14:53 +02:00
Daniel Schürmann
c65e880a65 radv: Implement nir_intrinsic_load_layer_id().
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-08 14:14:53 +02:00
Dave Airlie
1d327689f9 radv/gfx10: don't emit PFP packets on ME.
This was done for all previous GPUs.

This fixes Talos Principle launch hangs.

Fixes: 7e43022e8c (radv/gfx10: add gfx10_cs_emit_cache_flush)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-08 17:19:42 +10:00
Samuel Pitoiset
49e5136887 ac: select the GFX ring when halting waves with UMR on GFX10
GFX10 has two rings, so UMR want to know which one to halt.
Select the first one by default.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-08 09:10:57 +02:00
Bas Nieuwenhuizen
4d118ad44a radv/gfx10: Move NGG output handling outside of giant if-statement.
In merged shaders we put a big if around each shader, so both stages
can have a different number of threads. However, the NGG output code
still needs to run if the first shader is not executed.

This can happen when there are more gs threads than vs/es threads, or
when there are 0 es/vs threads (why? no clue).

Fixes: ee21bd7440 "radv/gfx10: implement NGG support (VS only)"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-08 01:49:54 +02:00
Bas Nieuwenhuizen
703efab7e4 radv: Actually use VK formats for the format table.
No ETC2 or ASTC on navi so nothing to add.

Fixes: 3dc5ec5d16 "radv/gfx10: generate gfx10_format_table.h"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-07 23:10:32 +02:00
Bas Nieuwenhuizen
e46b41b3ae radv: Handle cmask being disallowed by addrlib.
alignment=0 does weird things with align64.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-07-07 21:29:52 +02:00
Samuel Pitoiset
5eaed7ecfc radv/gfx10: enable support for NAVI10, NAVI12 and NAVI14
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Bas Nieuwenhuizen
817bd0cc2e radv/gfx10: Use GS rectlist when needed.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
ee21bd7440 radv/gfx10: implement NGG support (VS only)
This needs to be cleaned up a bit, and it probably contains
missing stuff and/or bugs.

This doesn't fix the "half of the triangles" issue.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Bas Nieuwenhuizen
9e37609d0b radv: Combine vs and tes output keys parts.
That way the same deref is valid for both shader stages.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-07 17:51:32 +02:00
Bas Nieuwenhuizen
d0978427cb radv/gfx10: Use new uconfig reg index packet for GFX10+.
Otherwise the hardware/firmware seems to not set the registers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-07 17:51:32 +02:00
Bas Nieuwenhuizen
aeb5b1a998 radv/gfx10: Set MEM_ORDERED flags on shaders.
Scattered because depending on stage they are at offset 24/25/27/30.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
67b6888d8b radv/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
74d69299d1 radv/gfx10: double the number of tessellation offchip buffers per SE
Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale
the number of offchip buffers accordingly.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
bf1e1a29c3 radv/gfx10: require LLVM 9+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
0f769ed398 radv/gfx10: disable geometry and tessellation shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
fe4419d3c7 radv/gfx10: disable binning
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
faf27ee9b3 radv/gfx10: disable CLEAR_STATE
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
698f9e6fd3 radv/gfx10: disable VK_EXT_transform_feedback
It requires a bunch of work, so disable for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
2141e6fc73 radv/gfx10: set user data base registers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
7e43022e8c radv/gfx10: add gfx10_cs_emit_cache_flush
The cache flush logic on GFX10 is quite different and it's
implemented with a new function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
b0b6e27bca radv/gfx10: set the DCC constant encoding flag
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
ce3b5d4c17 radv/gfx10: do not declare streamout SGPRS
Streamout is completely different on GFX10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
352365c5e2 radv/gfx10: do not set stream output shader config
Transform feedback is really different on GFX10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
3f68329806 radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initialization
The value doesn't need to be updated for tess.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
2a83154b4a radv/gfx10: update shader-related fields in si_emit_graphics()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
5556f16609 radv/gfx10: implement si_emit_compute()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
c90f46700d radv/gfx10: mask DCC tile swizzle by alignment
DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
b1b60a92b1 radv/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
12a42c2d9f radv/gfx10: implement radv_flush_vertex_descriptors() change
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:32 +02:00
Samuel Pitoiset
0ca09a7fe3 radv/gfx10: implement fill_geom_tess_rings()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:31 +02:00
Samuel Pitoiset
ebeb319f0e radv/gfx10: implement radv_CmdBindDescriptorSets()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:31 +02:00
Samuel Pitoiset
97891a0d10 radv/gfx10: implement write_buffer_descriptor()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:31 +02:00
Samuel Pitoiset
bdd8acde02 radv/gfx10: use the correct register for image descriptor dumping
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-07 17:51:31 +02:00