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radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initialization

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The value doesn't need to be updated for tess.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-06-25 15:38:44 +02:00 • committed by Bas Nieuwenhuizen
parent 2a83154b4a
commit 3f68329806
2 changed files with 3 additions and 1 deletions
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3
src/amd/vulkan/radv_pipeline.c
View file

@ -3434,7 +3434,8 @@ static void
radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
struct radv_pipeline *pipeline)
{
if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
pipeline->device->physical_device->rad_info.chip_class >= GFX10)
return;
unsigned vtx_reuse_depth = 30;

1
src/amd/vulkan/si_cmd_buffer.c
View file

@ -321,6 +321,7 @@ si_emit_graphics(struct radv_physical_device *physical_device,
}
if (physical_device->rad_info.chip_class >= GFX10) {
radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
physical_device->rad_info.pa_sc_tile_steering_override);
radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,