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radv/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-06-26 09:42:35 +02:00 • committed by Bas Nieuwenhuizen
parent 74d69299d1
commit 67b6888d8b
2 changed files with 44 additions and 4 deletions
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10
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2537,10 +2537,12 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
int32_t primitive_reset_en;
/* Draw state. */
si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
draw_info->indirect,
!!draw_info->strmout_buffer,
draw_info->indirect ? 0 : draw_info->count);
if (info->chip_class < GFX10) {
si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
draw_info->indirect,
!!draw_info->strmout_buffer,
draw_info->indirect ? 0 : draw_info->count);
}
/* Primitive restart. */
primitive_reset_en =

38
src/amd/vulkan/radv_pipeline.c
View file

@ -3513,6 +3513,41 @@ radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
return mask;
}
static void
gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
struct radv_pipeline *pipeline,
const struct radv_tessellation_state *tess,
const struct radv_gs_state *gs_state)
{
bool break_wave_at_eoi = false;
unsigned primgroup_size;
unsigned vertgroup_size;
if (radv_pipeline_has_tess(pipeline)) {
primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
vertgroup_size = 0;
} else if (radv_pipeline_has_gs(pipeline)) {
unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
} else {
primgroup_size = 128; /* recommended without a GS and tess */
vertgroup_size = 0;
}
if (radv_pipeline_has_tess(pipeline)) {
if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id ||
radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id)
break_wave_at_eoi = true;
}
radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
S_03096C_PRIM_GRP_SIZE(primgroup_size) |
S_03096C_VERT_GRP_SIZE(vertgroup_size) |
S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
}
static void
radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
@ -3543,6 +3578,9 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs);
radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE,
S_0286E8_WAVES(pipeline->max_waves) |
S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));