Commit graph

105005 commits

Author SHA1 Message Date
Alyssa Rosenzweig
dca0166ce1 pan/midgard: Implement load/store register classing
This does not yet support special->work spilling, nor does it support
multiclass breakup. These corner cases will be handled in succeeding
commits.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:37:22 -07:00
Alyssa Rosenzweig
839b80aa89 pan/midgard: Allocate special register classes
We'll want to also handle load/store and texture registers in our RA
loop.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:37:22 -07:00
Alyssa Rosenzweig
480b502443 pan/midgard: Move copy propagation into its own file
We also expose some utilities it uses as general MIR helpers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:37:22 -07:00
Alyssa Rosenzweig
b8caaa3000 pan/midgard: Add mir_simple_swizzle helper
Checks for x/xy/xyz/xyzw style swizzles (slightly more general but you
get the idea).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:37:21 -07:00
Alyssa Rosenzweig
63385a3fdb pan/midgard: Add mir_single_use helper
Helps as an optimization heuristic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:37:21 -07:00
Alyssa Rosenzweig
5534fdb7bf panfrost: Compute I/O counts from shader_info
...rather than exposing it in the vendored compiler region.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
4508f43eed panfrost: Don't DIY point size/coord fields
Again, it's in shader_info for us!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
bab4f6c724 panfrost: Use nir_gather_info information about discards
No need to track this ourselves!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
48991c7a1f panfrost: Use NIR helper invocations info
We don't need to guesstimate this ourselves. This will help when we
bringup derivatives.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
fb2fe6e7bc panfrost/sfbd: Flesh out fragment job
We include a zsbuf attachment function based on how the corresponding
MFBD code works, as well as extending cbufs to mipmapped rendering while
we're at it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:21 -07:00
Alyssa Rosenzweig
e6802af8c3 panfrost: Disable tiled formats on SFBD systems
Just because we don't have the format codes to render to them yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:20 -07:00
Alyssa Rosenzweig
990e24469c panfrost: Move require_sfbd to screen
We'll need it to specialize resource creation by chip.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:20 -07:00
Alyssa Rosenzweig
a9c73e825a panfrost: Reserve, but do not upload, shader padding
Fixes invalid read errors reported by valgrind.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 06:34:20 -07:00
Alyssa Rosenzweig
b2a3ca6bd5 util/ra: Add a getter for a node class
Complements the existing getters and the setter for node class. To be
used in the Panfrost RA refactor.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-07-25 06:14:12 -07:00
Tomeu Vizoso
688d9b4fb7 panfrost/ci: Update kernel to 5.2
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-25 15:08:44 +02:00
Nicolas Dufresne
08f1cefecd egl: Also query modifiers when exporting DMABuf
This fixes eglExportDMABUFImageQueryMESA() so it will report the
modififers of the underlying image. Without this information,
re-importing will likely be broken as it is rare these days that no
modifiers are used.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Fixes: 8f7338f284 ("egl: add initial EGL_MESA_image_dma_buf_export v2.4")
2019-07-25 05:14:36 +00:00
Heinrich Fink
4886924262 mesa: Enable GL_MESA_framebuffer_flip_y for GL 4.3
Extend MESA_framebuffer_flip_y to be used with OpenGL versions 4.3 and
higher. OpenGL 4.3 adds FramebufferParameteri needed by this extension.

Reviewed-by: Fritz Koenig <frkoenig@google.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-25 04:47:38 +00:00
Alyssa Rosenzweig
31c9fcbd0f panfrost: Don't expose some atomic stuff even with dEQP
Fixes dEQP crashes.

Fixes: 2f93ecd654 ("panfrost: Fake CAPs for dEQP-GLES31")

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-07-24 17:21:12 -07:00
Dave Airlie
16fcbb2eba gallium: fix windows build from params change.
This is why we can't have nice things. I'm sure there's someway
to do this with {0} but I really don't have time for that.

Fixes: 2631fd3b0b ("gallivm: rework lp_build_tgsi_soa to take a struct")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-25 10:02:22 +10:00
Jonathan Marek
97c8314c5f nir/algebraic: add scmp algebraic optimizations
When 'x' is the result of a scmp op:

x != 0.0 or x == 1.0: passthrough
x == 0.0 or x != 1.0: invert

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Jonathan Marek
9be902097c nir/algebraic: add option to lower fall_equalN/fany_nequalN
Add generic lowerings for fall_equalN/fany_nequalN. These should be optimal
for vec4 backends that doesn't have any special instructions for it, as
long as they support saturate.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Jonathan Marek
397375d3f3 nir/algebraic: add fdot2 optimizations
Add simple fdot2 optimizations that are missing.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Jonathan Marek
1e089d0575 nir/algebraic: add option to lower fdph
For backends that don't have a 'fdph' instructions

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Jonathan Marek
bc3b6168ba nir: replace lower_sincos with algebraic opt
This version has less ops for the same precision.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Jonathan Marek
5a4e71c082 nir/algebraic: allow swizzle in nir_algebraic replace expression
This is to allow optimizations in nir_opt_algebraic not otherwise possible

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2019-07-24 17:36:21 -04:00
Rob Clark
b4f4768672 gallium/u_transfer_helper: fix assert in RGTC case
Previously we'd hit the unreachable() for uploading RGTC.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-24 21:11:06 +00:00
Yevhenii Kolesnikov
53730ab32c main: Free memory allocated for gl_bitmap_atlas structure
Structure itself wasn't freed during context tear-down, causing a
memory leak on iris.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-07-24 15:31:26 -04:00
Daniel Schürmann
e272fdd508 nir,intel: lower if (cond) demote() to new intrinsic demote_if(cond)
This will effectively enable the optimization in anv.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-07-24 13:02:18 -05:00
Kenneth Graunke
517005b4cf i965: Use NIR to lower legacy userclipping.
This allows us to drop legacy userclip plane handling in both the vec4
and FS backends, and simplifies a few interfaces.

v2 (Jason Ekstrand):
 - Move brw_nir_lower_legacy_clipping to brw_nir_uniforms.cpp because
   it's i965-specific.
 - Handle adding the params in brw_nir_lower_legacy_clipping
 - Call brw_nir_lower_legacy_clipping from brw_codegen_vs_prog

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-07-24 18:00:13 +00:00
Jason Ekstrand
d10de25309 anv: Implement VK_EXT_subgroup_size_control
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
bcef32d49b anv/pipeline: Plumb pipeline shader stage create flags
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
2a236c76f8 intel/compiler: Allow for required subgroup sizes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
4397eb91c1 intel/compiler: Allow for varying subgroup sizes
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
799f0f7b28 nir/lower_subgroups: Properly lower masks when subgroup_size == 0
Instead of building a constant mask (which depends on knowing the
subgroup size), we build an expression.  Because the pass uses the
nir_shader_lower_instructions helper, subgroup lowering will be run on
any newly emitted instructions as well as the previously existing
instructions.  In particular, if the subgroup size is known, the newly
emitted subgroup_size intrinsic will get turned into a constant and a
later constant folding pass will clean it up.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
256e6c2d94 vulkan: Update the XML and headers to 1.1.116
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
c84b8eeeac intel/compiler: Be more conservative about subgroup sizes in GL
The rules for gl_SubgroupSize in Vulkan require that it be a constant
that can be queried through the API.  However, all GL requires is that
it's a uniform.  Instead of always claiming that the subgroup size in
the shader is 32 in GL like we have to do for Vulkan, claim 8 for
geometry stages, the maximum for fragment shaders, and the actual size
for compute.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
1981460af2 intel/compiler: Lower gl_SubgroupSize in postprocess_nir
Instead of lowering the subgroup size so early, wait until we have more
information.  In particular, we're going to want different subgroup
sizes from different stages depending on the API.  We also defer
lowering of subgroup masks because the ge/gt masks require the subgroup
size to generate a subgroup mask.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Jason Ekstrand
f62227f2b7 intel/nir: Make brw_nir_apply_sampler_key more generic
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-07-24 12:55:40 -05:00
Sagar Ghuge
87cef718e1 nir: Add lowering for nir_op_irem and nir_op_imod
Tested on Gen > 9.

v2: 1) Fix lowering
    2) Keep a consistent i/u order (Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-24 10:33:09 -07:00
Yevhenii Kolesnikov
882fe09a74 main: Fix memleaks in mesa_use_program
Add freeing of SubroutineIndexes to the _mesa_free_shader_state.

Fixes: 4566aaaa5b ("mesa/subroutines: start adding per-context
subroutine index support (v1.1)")
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-24 16:54:21 +00:00
Andrii Simiklit
fa2fc68de1 intel/compiler: don't use a keyword struct for a class fs_reg
warning: struct 'fs_reg' was previously declared as a class
Fixes: e64be391 ("intel/compiler: generalize the combine constants pass")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
2019-07-24 13:26:42 +00:00
Qiang Yu
280dfa02fa lima/ppir: fix disassembler temp read/write print
temp read/write use negtive offset, and handle
alignment==1 case.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-07-24 20:39:39 +08:00
Eric Engestrom
e7e31b18d6 gallium+mesa: fix tgsi_semantic array type
Fixes: ed23335a31 ("gallium: use enums in p_shader_tokens.h (v2)")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-24 09:33:29 +01:00
Eric Engestrom
f986741a91 util: fix no-op macro (bad number of arguments)
Fixes: b8e077daee ("util: no-op __builtin_types_compatible_p() for non-GCC compilers")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-07-24 09:13:58 +01:00
Samuel Pitoiset
4389e85dc9 radv/gfx10: enable VK_EXT_transform_feedback
When a pipeline uses transform feedback, the driver fallbacks to
the legacy path because NGG support for streamout is a non-trivial
amount of work.

AMDVLK also uses the legacy path for streamout, while RadeonSI
uses the new NGG path.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-24 08:23:37 +02:00
Samuel Pitoiset
a3a4fa1860 radv/gfx10: do not enable NGG if a pipeline uses XFB
NGG GS for streamout requires a bunch of work, so enable it with
the legacy path only for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-24 08:23:34 +02:00
Samuel Pitoiset
09abe571a2 radv/gfx10: emit streamout shader config
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-24 08:23:32 +02:00
Samuel Pitoiset
383c2e625a radv/gfx10: declare streamout user SGPRs
Required for legacy streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-24 08:23:30 +02:00
Samuel Pitoiset
fd195d8085 radv/gfx10: update streamout descriptors
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-24 08:23:27 +02:00
Samuel Pitoiset
ea337c8b7e radv/gfx10: fix VS input VGPRs with the legacy path
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-24 08:23:21 +02:00